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arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-khadas-edge2
The board exposes the GPIO4_B1 pin to control the voltage bias on the HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI 1.4/2.0 TMDS mode. Wire up the hdmi0 node to its dedicated GPIO via frl-enable-gpios to allow adjusting the bias when transitioning between TMDS and FRL modes. While at it, remove the duplicated &hdmi0_sound node. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-7-924df9db884a@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -194,6 +194,10 @@ &gpu {
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};
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&hdmi0 {
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frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
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&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
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pinctrl-names = "default";
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status = "okay";
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};
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@ -217,10 +221,6 @@ &hdptxphy0 {
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status = "okay";
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};
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&hdmi0_sound {
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0m2_xfer>;
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@ -282,6 +282,12 @@ &pd_gpu {
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};
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&pinctrl {
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hdmi {
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hdmi0_tx_on_h: hdmi0-tx-on-h {
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rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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vdd_sd {
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vdd_sd_en: vdd-sd-en {
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rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
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