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https://github.com/torvalds/linux.git
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Merge branch 'pci/controller/xilinx'
- Fix off-by-one error in INTx IRQ handler that caused INTx interrupts to be lost or delivered as the wrong interrupt (Sean Anderson) - Rate-limit misc interrupt messages (Sean Anderson) - Turn off the clock on probe failure and device removal (Sean Anderson) - Add DT binding and driver support for enabling/disabling PHYs (Sean Anderson) - Add PCIe phy bindings for the ZCU102 (Sean Anderson) - Add support for Xilinx QDMA Soft IP PCIe Root Port Bridge to DT binding and xilinx-dma-pl driver (Thippeswamy Havalige) * pci/controller/xilinx: PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge arm64: zynqmp: Add PCIe phys property for ZCU102 PCI: xilinx-nwl: Add PHY support dt-bindings: pci: xilinx-nwl: Add phys property PCI: xilinx-nwl: Clean up clock on probe failure/removal PCI: xilinx-nwl: Rate-limit misc interrupt messages PCI: xilinx-nwl: Fix register misspelling PCI: xilinx-nwl: Fix off-by-one in INTx IRQ handler
This commit is contained in:
Bjorn Helgaas
commit
bb78146c18
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@ -61,6 +61,11 @@ properties:
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interrupt-map:
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maxItems: 4
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phys:
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minItems: 1
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maxItems: 4
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description: One phy per logical lane, in order
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power-domains:
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maxItems: 1
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@ -110,6 +115,7 @@ examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/xlnx-zynqmp-power.h>
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soc {
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#address-cells = <2>;
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@ -138,6 +144,7 @@ examples:
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<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
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<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
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msi-parent = <&nwl_pcie>;
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phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
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power-domains = <&zynqmp_firmware PD_PCIE>;
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iommus = <&smmu 0x4d0>;
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pcie_intc: legacy-interrupt-controller {
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@ -14,10 +14,21 @@ allOf:
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properties:
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compatible:
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const: xlnx,xdma-host-3.00
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enum:
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- xlnx,xdma-host-3.00
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- xlnx,qdma-host-3.00
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reg:
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maxItems: 1
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items:
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- description: configuration region and XDMA bridge register.
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- description: QDMA bridge register.
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minItems: 1
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reg-names:
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items:
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- const: cfg
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- const: breg
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minItems: 1
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ranges:
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maxItems: 2
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@ -76,6 +87,27 @@ required:
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- "#interrupt-cells"
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- interrupt-controller
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if:
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properties:
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compatible:
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contains:
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enum:
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- xlnx,qdma-host-3.00
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then:
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properties:
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reg:
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minItems: 2
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reg-names:
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minItems: 2
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required:
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- reg-names
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else:
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properties:
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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unevaluatedProperties: false
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examples:
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@ -941,6 +941,7 @@ conf-pull-none {
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&pcie {
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status = "okay";
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phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
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};
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&psgtr {
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@ -71,10 +71,24 @@
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/* Phy Status/Control Register definitions */
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#define XILINX_PCIE_DMA_REG_PSCR_LNKUP BIT(11)
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#define QDMA_BRIDGE_BASE_OFF 0xcd8
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/* Number of MSI IRQs */
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#define XILINX_NUM_MSI_IRQS 64
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enum xilinx_pl_dma_version {
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XDMA,
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QDMA,
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};
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/**
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* struct xilinx_pl_dma_variant - PL DMA PCIe variant information
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* @version: DMA version
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*/
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struct xilinx_pl_dma_variant {
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enum xilinx_pl_dma_version version;
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};
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struct xilinx_msi {
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struct irq_domain *msi_domain;
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unsigned long *bitmap;
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@ -88,6 +102,7 @@ struct xilinx_msi {
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* struct pl_dma_pcie - PCIe port information
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* @dev: Device pointer
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* @reg_base: IO Mapped Register Base
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* @cfg_base: IO Mapped Configuration Base
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* @irq: Interrupt number
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* @cfg: Holds mappings of config space window
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* @phys_reg_base: Physical address of reg base
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@ -97,10 +112,12 @@ struct xilinx_msi {
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* @msi: MSI information
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* @intx_irq: INTx error interrupt number
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* @lock: Lock protecting shared register access
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* @variant: PL DMA PCIe version check pointer
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*/
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struct pl_dma_pcie {
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struct device *dev;
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void __iomem *reg_base;
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void __iomem *cfg_base;
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int irq;
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struct pci_config_window *cfg;
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phys_addr_t phys_reg_base;
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@ -110,16 +127,23 @@ struct pl_dma_pcie {
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struct xilinx_msi msi;
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int intx_irq;
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raw_spinlock_t lock;
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const struct xilinx_pl_dma_variant *variant;
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};
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static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg)
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{
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if (port->variant->version == QDMA)
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return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF);
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return readl(port->reg_base + reg);
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}
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static inline void pcie_write(struct pl_dma_pcie *port, u32 val, u32 reg)
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{
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writel(val, port->reg_base + reg);
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if (port->variant->version == QDMA)
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writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF);
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else
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writel(val, port->reg_base + reg);
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}
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static inline bool xilinx_pl_dma_pcie_link_up(struct pl_dma_pcie *port)
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@ -173,6 +197,9 @@ static void __iomem *xilinx_pl_dma_pcie_map_bus(struct pci_bus *bus,
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if (!xilinx_pl_dma_pcie_valid_device(bus, devfn))
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return NULL;
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if (port->variant->version == QDMA)
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return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
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return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
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}
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@ -724,6 +751,15 @@ static int xilinx_pl_dma_pcie_parse_dt(struct pl_dma_pcie *port,
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port->reg_base = port->cfg->win;
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if (port->variant->version == QDMA) {
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port->cfg_base = port->cfg->win;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
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port->reg_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(port->reg_base))
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return PTR_ERR(port->reg_base);
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port->phys_reg_base = res->start;
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}
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err = xilinx_request_msi_irq(port);
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if (err) {
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pci_ecam_free(port->cfg);
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@ -753,6 +789,8 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev)
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if (!bus)
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return -ENODEV;
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port->variant = of_device_get_match_data(dev);
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err = xilinx_pl_dma_pcie_parse_dt(port, bus->res);
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if (err) {
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dev_err(dev, "Parsing DT failed\n");
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@ -784,9 +822,22 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev)
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return err;
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}
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static const struct xilinx_pl_dma_variant xdma_host = {
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.version = XDMA,
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};
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static const struct xilinx_pl_dma_variant qdma_host = {
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.version = QDMA,
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};
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static const struct of_device_id xilinx_pl_dma_pcie_of_match[] = {
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{
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.compatible = "xlnx,xdma-host-3.00",
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.data = &xdma_host,
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},
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{
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.compatible = "xlnx,qdma-host-3.00",
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.data = &qdma_host,
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},
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{}
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};
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@ -19,6 +19,7 @@
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/irqchip/chained_irq.h>
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@ -80,8 +81,8 @@
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#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
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#define MSGF_MISC_SR_FATAL_DEV BIT(23)
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#define MSGF_MISC_SR_LINK_DOWN BIT(24)
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#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
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#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
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#define MSGF_MISC_SR_LINK_AUTO_BWIDTH BIT(25)
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#define MSGF_MISC_SR_LINK_BWIDTH BIT(26)
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#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
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MSGF_MISC_SR_RXMSG_OVER | \
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@ -96,8 +97,8 @@
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MSGF_MISC_SR_NON_FATAL_DEV | \
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MSGF_MISC_SR_FATAL_DEV | \
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MSGF_MISC_SR_LINK_DOWN | \
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MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
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MSGF_MSIC_SR_LINK_BWIDTH)
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MSGF_MISC_SR_LINK_AUTO_BWIDTH | \
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MSGF_MISC_SR_LINK_BWIDTH)
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/* Legacy interrupt status mask bits */
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#define MSGF_LEG_SR_INTA BIT(0)
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@ -157,6 +158,7 @@ struct nwl_pcie {
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void __iomem *breg_base;
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void __iomem *pcireg_base;
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void __iomem *ecam_base;
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struct phy *phy[4];
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phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
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phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
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phys_addr_t phys_ecam_base; /* Physical Configuration Base */
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@ -267,42 +269,42 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
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return IRQ_NONE;
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if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
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dev_err(dev, "Received Message FIFO Overflow\n");
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dev_err_ratelimited(dev, "Received Message FIFO Overflow\n");
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if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
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dev_err(dev, "Slave error\n");
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dev_err_ratelimited(dev, "Slave error\n");
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if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
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dev_err(dev, "Master error\n");
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dev_err_ratelimited(dev, "Master error\n");
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if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
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dev_err(dev, "In Misc Ingress address translation error\n");
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dev_err_ratelimited(dev, "In Misc Ingress address translation error\n");
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if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
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dev_err(dev, "In Misc Egress address translation error\n");
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dev_err_ratelimited(dev, "In Misc Egress address translation error\n");
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|
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if (misc_stat & MSGF_MISC_SR_FATAL_AER)
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dev_err(dev, "Fatal Error in AER Capability\n");
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dev_err_ratelimited(dev, "Fatal Error in AER Capability\n");
|
||||
|
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if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
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dev_err(dev, "Non-Fatal Error in AER Capability\n");
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dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n");
|
||||
|
||||
if (misc_stat & MSGF_MISC_SR_CORR_AER)
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dev_err(dev, "Correctable Error in AER Capability\n");
|
||||
dev_err_ratelimited(dev, "Correctable Error in AER Capability\n");
|
||||
|
||||
if (misc_stat & MSGF_MISC_SR_UR_DETECT)
|
||||
dev_err(dev, "Unsupported request Detected\n");
|
||||
dev_err_ratelimited(dev, "Unsupported request Detected\n");
|
||||
|
||||
if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
|
||||
dev_err(dev, "Non-Fatal Error Detected\n");
|
||||
dev_err_ratelimited(dev, "Non-Fatal Error Detected\n");
|
||||
|
||||
if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
|
||||
dev_err(dev, "Fatal Error Detected\n");
|
||||
dev_err_ratelimited(dev, "Fatal Error Detected\n");
|
||||
|
||||
if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
|
||||
if (misc_stat & MSGF_MISC_SR_LINK_AUTO_BWIDTH)
|
||||
dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
|
||||
|
||||
if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
|
||||
if (misc_stat & MSGF_MISC_SR_LINK_BWIDTH)
|
||||
dev_info(dev, "Link Bandwidth Management Status bit set\n");
|
||||
|
||||
/* Clear misc interrupt status */
|
||||
|
|
@ -371,7 +373,7 @@ static void nwl_mask_intx_irq(struct irq_data *data)
|
|||
u32 mask;
|
||||
u32 val;
|
||||
|
||||
mask = 1 << (data->hwirq - 1);
|
||||
mask = 1 << data->hwirq;
|
||||
raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
|
||||
val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
|
||||
nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
|
||||
|
|
@ -385,7 +387,7 @@ static void nwl_unmask_intx_irq(struct irq_data *data)
|
|||
u32 mask;
|
||||
u32 val;
|
||||
|
||||
mask = 1 << (data->hwirq - 1);
|
||||
mask = 1 << data->hwirq;
|
||||
raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
|
||||
val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
|
||||
nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
|
||||
|
|
@ -514,6 +516,60 @@ static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void nwl_pcie_phy_power_off(struct nwl_pcie *pcie, int i)
|
||||
{
|
||||
int err = phy_power_off(pcie->phy[i]);
|
||||
|
||||
if (err)
|
||||
dev_err(pcie->dev, "could not power off phy %d (err=%d)\n", i,
|
||||
err);
|
||||
}
|
||||
|
||||
static void nwl_pcie_phy_exit(struct nwl_pcie *pcie, int i)
|
||||
{
|
||||
int err = phy_exit(pcie->phy[i]);
|
||||
|
||||
if (err)
|
||||
dev_err(pcie->dev, "could not exit phy %d (err=%d)\n", i, err);
|
||||
}
|
||||
|
||||
static int nwl_pcie_phy_enable(struct nwl_pcie *pcie)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
|
||||
ret = phy_init(pcie->phy[i]);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = phy_power_on(pcie->phy[i]);
|
||||
if (ret) {
|
||||
nwl_pcie_phy_exit(pcie, i);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
while (i--) {
|
||||
nwl_pcie_phy_power_off(pcie, i);
|
||||
nwl_pcie_phy_exit(pcie, i);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void nwl_pcie_phy_disable(struct nwl_pcie *pcie)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = ARRAY_SIZE(pcie->phy); i--;) {
|
||||
nwl_pcie_phy_power_off(pcie, i);
|
||||
nwl_pcie_phy_exit(pcie, i);
|
||||
}
|
||||
}
|
||||
|
||||
static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
|
||||
{
|
||||
struct device *dev = pcie->dev;
|
||||
|
|
@ -725,6 +781,7 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
|
|||
{
|
||||
struct device *dev = pcie->dev;
|
||||
struct resource *res;
|
||||
int i;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
|
||||
pcie->breg_base = devm_ioremap_resource(dev, res);
|
||||
|
|
@ -752,6 +809,18 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
|
|||
irq_set_chained_handler_and_data(pcie->irq_intx,
|
||||
nwl_pcie_leg_handler, pcie);
|
||||
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
|
||||
pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i);
|
||||
if (PTR_ERR(pcie->phy[i]) == -ENODEV) {
|
||||
pcie->phy[i] = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (IS_ERR(pcie->phy[i]))
|
||||
return PTR_ERR(pcie->phy[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -772,6 +841,7 @@ static int nwl_pcie_probe(struct platform_device *pdev)
|
|||
return -ENODEV;
|
||||
|
||||
pcie = pci_host_bridge_priv(bridge);
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
pcie->dev = dev;
|
||||
|
||||
|
|
@ -791,16 +861,22 @@ static int nwl_pcie_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
}
|
||||
|
||||
err = nwl_pcie_phy_enable(pcie);
|
||||
if (err) {
|
||||
dev_err(dev, "could not enable PHYs\n");
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
err = nwl_pcie_bridge_init(pcie);
|
||||
if (err) {
|
||||
dev_err(dev, "HW Initialization failed\n");
|
||||
return err;
|
||||
goto err_phy;
|
||||
}
|
||||
|
||||
err = nwl_pcie_init_irq_domain(pcie);
|
||||
if (err) {
|
||||
dev_err(dev, "Failed creating IRQ Domain\n");
|
||||
return err;
|
||||
goto err_phy;
|
||||
}
|
||||
|
||||
bridge->sysdata = pcie;
|
||||
|
|
@ -810,11 +886,27 @@ static int nwl_pcie_probe(struct platform_device *pdev)
|
|||
err = nwl_pcie_enable_msi(pcie);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to enable MSI support: %d\n", err);
|
||||
return err;
|
||||
goto err_phy;
|
||||
}
|
||||
}
|
||||
|
||||
return pci_host_probe(bridge);
|
||||
err = pci_host_probe(bridge);
|
||||
if (!err)
|
||||
return 0;
|
||||
|
||||
err_phy:
|
||||
nwl_pcie_phy_disable(pcie);
|
||||
err_clk:
|
||||
clk_disable_unprepare(pcie->clk);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void nwl_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct nwl_pcie *pcie = platform_get_drvdata(pdev);
|
||||
|
||||
nwl_pcie_phy_disable(pcie);
|
||||
clk_disable_unprepare(pcie->clk);
|
||||
}
|
||||
|
||||
static struct platform_driver nwl_pcie_driver = {
|
||||
|
|
@ -824,5 +916,6 @@ static struct platform_driver nwl_pcie_driver = {
|
|||
.of_match_table = nwl_pcie_of_match,
|
||||
},
|
||||
.probe = nwl_pcie_probe,
|
||||
.remove_new = nwl_pcie_remove,
|
||||
};
|
||||
builtin_platform_driver(nwl_pcie_driver);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user