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Merge "spmi: add SPMI PMIC arbiter debug bus driver"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
bb2cf3decd
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@ -34,6 +34,16 @@ config SPMI_MSM_PMIC_ARB
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This is required for communicating with Qualcomm PMICs and
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other devices that have the SPMI interface.
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config SPMI_MSM_PMIC_ARB_DEBUG
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tristate "QTI SPMI Debug Controller (PMIC Arbiter)"
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depends on ARCH_QCOM || COMPILE_TEST
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depends on HAS_IOMEM
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help
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If you say yes to this option, support will be included for the
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built-in SPMI PMIC Arbiter debug interface on Qualcomm Technologies,
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Inc. (QTI) MSM family processors. This feature is available on chips
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with PMIC arbiter version 5 and above.
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config SPMI_MTK_PMIF
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tristate "Mediatek SPMI Controller (PMIC Arbiter)"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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@ -6,5 +6,6 @@ obj-$(CONFIG_SPMI) += spmi.o
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obj-$(CONFIG_SPMI_HISI3670) += hisi-spmi-controller.o
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obj-$(CONFIG_SPMI_MSM_PMIC_ARB) += spmi-pmic-arb.o
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obj-$(CONFIG_SPMI_MSM_PMIC_ARB_DEBUG) += spmi-pmic-arb-debug.o
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obj-$(CONFIG_SPMI_MTK_PMIF) += spmi-mtk-pmif.o
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obj-$(CONFIG_SPMI_QTI_GLINK_DEBUG) += spmi-glink-debug.o
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344
drivers/spmi/spmi-pmic-arb-debug.c
Normal file
344
drivers/spmi/spmi-pmic-arb-debug.c
Normal file
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@ -0,0 +1,344 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. */
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spmi.h>
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/* PMIC Arbiter debug register offsets */
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#define PMIC_ARB_DEBUG_CMD0 0x00
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#define PMIC_ARB_DEBUG_CMD1 0x04
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#define PMIC_ARB_DEBUG_CMD2 0x08
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#define PMIC_ARB_DEBUG_CMD3 0x0C
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#define PMIC_ARB_DEBUG_STATUS 0x14
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#define PMIC_ARB_DEBUG_WDATA(n) (0x18 + 4 * (n))
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#define PMIC_ARB_DEBUG_RDATA(n) (0x38 + 4 * (n))
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/* Transaction status flag bits */
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enum pmic_arb_chnl_status {
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PMIC_ARB_STATUS_DONE = BIT(0),
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PMIC_ARB_STATUS_FAILURE = BIT(1),
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PMIC_ARB_STATUS_DENIED = BIT(2),
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PMIC_ARB_STATUS_DROPPED = BIT(3),
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};
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/* Command Opcodes */
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enum pmic_arb_cmd_op_code {
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PMIC_ARB_OP_EXT_WRITEL = 0,
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PMIC_ARB_OP_EXT_READL = 1,
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PMIC_ARB_OP_EXT_WRITE = 2,
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PMIC_ARB_OP_RESET = 3,
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PMIC_ARB_OP_SLEEP = 4,
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PMIC_ARB_OP_SHUTDOWN = 5,
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PMIC_ARB_OP_WAKEUP = 6,
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PMIC_ARB_OP_AUTHENTICATE = 7,
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PMIC_ARB_OP_MSTR_READ = 8,
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PMIC_ARB_OP_MSTR_WRITE = 9,
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PMIC_ARB_OP_EXT_READ = 13,
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PMIC_ARB_OP_WRITE = 14,
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PMIC_ARB_OP_READ = 15,
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PMIC_ARB_OP_ZERO_WRITE = 16,
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};
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#define PMIC_ARB_TIMEOUT_US 100
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#define PMIC_ARB_MAX_TRANS_BYTES 8
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#define PMIC_ARB_MAX_SID 0xF
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/**
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* spmi_pmic_arb_debug - SPMI PMIC Arbiter debug object
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*
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* @addr: base address of SPMI PMIC arbiter debug module
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* @lock: lock to synchronize accesses.
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*/
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struct spmi_pmic_arb_debug {
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void __iomem *addr;
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raw_spinlock_t lock;
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};
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static inline void pmic_arb_debug_write(struct spmi_pmic_arb_debug *pa,
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u32 offset, u32 val)
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{
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writel_relaxed(val, pa->addr + offset);
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}
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static inline u32 pmic_arb_debug_read(struct spmi_pmic_arb_debug *pa,
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u32 offset)
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{
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return readl_relaxed(pa->addr + offset);
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}
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/* pa->lock must be held by the caller. */
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static int pmic_arb_debug_wait_for_done(struct spmi_controller *ctrl)
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{
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struct spmi_pmic_arb_debug *pa = spmi_controller_get_drvdata(ctrl);
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u32 status = 0;
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u32 timeout = PMIC_ARB_TIMEOUT_US;
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while (timeout--) {
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status = pmic_arb_debug_read(pa, PMIC_ARB_DEBUG_STATUS);
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if (status & PMIC_ARB_STATUS_DONE) {
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if (status & PMIC_ARB_STATUS_DENIED) {
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dev_err(&ctrl->dev, "%s: transaction denied (0x%x)\n",
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__func__, status);
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return -EPERM;
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}
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if (status & PMIC_ARB_STATUS_FAILURE) {
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dev_err(&ctrl->dev, "%s: transaction failed (0x%x)\n",
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__func__, status);
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return -EIO;
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}
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if (status & PMIC_ARB_STATUS_DROPPED) {
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dev_err(&ctrl->dev, "%s: transaction dropped (0x%x)\n",
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__func__, status);
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return -EIO;
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}
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return 0;
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}
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udelay(1);
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}
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dev_err(&ctrl->dev, "%s: timeout, status 0x%x\n", __func__, status);
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return -ETIMEDOUT;
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}
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/* pa->lock must be held by the caller. */
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static int pmic_arb_debug_issue_command(struct spmi_controller *ctrl, u8 opc,
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u8 sid, u16 addr, size_t len)
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{
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struct spmi_pmic_arb_debug *pa = spmi_controller_get_drvdata(ctrl);
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u16 pid = (addr >> 8) & 0xFF;
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u16 offset = addr & 0xFF;
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u8 byte_count = len - 1;
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if (byte_count >= PMIC_ARB_MAX_TRANS_BYTES) {
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dev_err(&ctrl->dev, "pmic-arb supports 1 to %d bytes per transaction, but %zu requested\n",
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PMIC_ARB_MAX_TRANS_BYTES, len);
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return -EINVAL;
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}
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if (sid > PMIC_ARB_MAX_SID) {
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dev_err(&ctrl->dev, "pmic-arb supports sid 0 to %u, but %u requested\n",
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PMIC_ARB_MAX_SID, sid);
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return -EINVAL;
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}
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pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_CMD3, offset);
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pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_CMD2, pid);
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pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_CMD1, (byte_count << 4) | sid);
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/* Start the transaction */
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pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_CMD0, opc << 1);
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return pmic_arb_debug_wait_for_done(ctrl);
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}
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/* Non-data command */
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static int pmic_arb_debug_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
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{
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dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
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/* Check for valid non-data command */
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if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
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return -EINVAL;
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return -EOPNOTSUPP;
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}
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static int pmic_arb_debug_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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u16 addr, u8 *buf, size_t len)
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{
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struct spmi_pmic_arb_debug *pa = spmi_controller_get_drvdata(ctrl);
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unsigned long flags;
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int i, rc;
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/* Check the opcode */
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if (opc >= 0x60 && opc <= 0x7F)
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opc = PMIC_ARB_OP_READ;
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else if (opc >= 0x20 && opc <= 0x2F)
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opc = PMIC_ARB_OP_EXT_READ;
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else if (opc >= 0x38 && opc <= 0x3F)
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opc = PMIC_ARB_OP_EXT_READL;
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else
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return -EINVAL;
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raw_spin_lock_irqsave(&pa->lock, flags);
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rc = pmic_arb_debug_issue_command(ctrl, opc, sid, addr, len);
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if (rc)
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goto done;
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/* Read data from FIFO */
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for (i = 0; i < len; i++)
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buf[i] = pmic_arb_debug_read(pa, PMIC_ARB_DEBUG_RDATA(i));
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done:
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raw_spin_unlock_irqrestore(&pa->lock, flags);
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return rc;
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}
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static int pmic_arb_debug_write_cmd(struct spmi_controller *ctrl, u8 opc,
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u8 sid, u16 addr, const u8 *buf, size_t len)
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{
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struct spmi_pmic_arb_debug *pa = spmi_controller_get_drvdata(ctrl);
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unsigned long flags;
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int i, rc;
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if (len > PMIC_ARB_MAX_TRANS_BYTES) {
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dev_err(&ctrl->dev, "pmic-arb supports 1 to %d bytes per transaction, but %zu requested\n",
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PMIC_ARB_MAX_TRANS_BYTES, len);
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return -EINVAL;
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}
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/* Check the opcode */
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if (opc >= 0x40 && opc <= 0x5F)
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opc = PMIC_ARB_OP_WRITE;
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else if (opc >= 0x00 && opc <= 0x0F)
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opc = PMIC_ARB_OP_EXT_WRITE;
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else if (opc >= 0x30 && opc <= 0x37)
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opc = PMIC_ARB_OP_EXT_WRITEL;
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else if (opc >= 0x80)
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opc = PMIC_ARB_OP_ZERO_WRITE;
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else
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return -EINVAL;
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raw_spin_lock_irqsave(&pa->lock, flags);
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/* Write data to FIFO */
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for (i = 0; i < len; i++)
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pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_WDATA(i), buf[i]);
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rc = pmic_arb_debug_issue_command(ctrl, opc, sid, addr, len);
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raw_spin_unlock_irqrestore(&pa->lock, flags);
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return rc;
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}
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static int spmi_pmic_arb_debug_probe(struct platform_device *pdev)
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{
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struct spmi_pmic_arb_debug *pa;
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struct spmi_controller *ctrl;
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struct resource *res;
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int rc;
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u32 fuse_val, fuse_bit;
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void __iomem *fuse_addr;
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/* Check if the debug bus is disabled by a fuse. */
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rc = of_property_read_u32(pdev->dev.of_node, "qcom,fuse-disable-bit",
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&fuse_bit);
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if (!rc) {
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if (fuse_bit > 31) {
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dev_err(&pdev->dev, "qcom,fuse-disable-bit supports values 0 to 31, but %u specified\n",
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fuse_bit);
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return -EINVAL;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"fuse");
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if (!res) {
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dev_err(&pdev->dev, "fuse address not specified\n");
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return -EINVAL;
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}
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fuse_addr = ioremap(res->start, resource_size(res));
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if (!fuse_addr)
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return -EINVAL;
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fuse_val = readl_relaxed(fuse_addr);
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iounmap(fuse_addr);
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if (fuse_val & BIT(fuse_bit)) {
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dev_err(&pdev->dev, "SPMI PMIC arbiter debug bus disabled by fuse\n");
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return -ENODEV;
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}
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}
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ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa));
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if (!ctrl)
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return -ENOMEM;
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pa = spmi_controller_get_drvdata(ctrl);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
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if (!res) {
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dev_err(&pdev->dev, "core address not specified\n");
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rc = -EINVAL;
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goto err_put_ctrl;
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}
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pa->addr = devm_ioremap_resource(&ctrl->dev, res);
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if (IS_ERR(pa->addr)) {
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rc = PTR_ERR(pa->addr);
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goto err_put_ctrl;
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}
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platform_set_drvdata(pdev, ctrl);
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raw_spin_lock_init(&pa->lock);
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ctrl->cmd = pmic_arb_debug_cmd;
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ctrl->read_cmd = pmic_arb_debug_read_cmd;
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ctrl->write_cmd = pmic_arb_debug_write_cmd;
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rc = spmi_controller_add(ctrl);
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if (rc)
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goto err_put_ctrl;
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dev_info(&ctrl->dev, "SPMI PMIC arbiter debug bus controller added\n");
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return 0;
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err_put_ctrl:
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spmi_controller_put(ctrl);
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return rc;
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}
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static int spmi_pmic_arb_debug_remove(struct platform_device *pdev)
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{
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struct spmi_controller *ctrl = platform_get_drvdata(pdev);
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spmi_controller_remove(ctrl);
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spmi_controller_put(ctrl);
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return 0;
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}
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static const struct of_device_id spmi_pmic_arb_debug_match_table[] = {
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{ .compatible = "qcom,spmi-pmic-arb-debug", },
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{},
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};
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MODULE_DEVICE_TABLE(of, spmi_pmic_arb_debug_match_table);
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static struct platform_driver spmi_pmic_arb_debug_driver = {
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.probe = spmi_pmic_arb_debug_probe,
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.remove = spmi_pmic_arb_debug_remove,
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.driver = {
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.name = "spmi_pmic_arb_debug",
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.of_match_table = spmi_pmic_arb_debug_match_table,
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},
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};
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int __init spmi_pmic_arb_debug_init(void)
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{
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return platform_driver_register(&spmi_pmic_arb_debug_driver);
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}
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arch_initcall(spmi_pmic_arb_debug_init);
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static void __exit spmi_pmic_arb_debug_exit(void)
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{
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platform_driver_unregister(&spmi_pmic_arb_debug_driver);
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}
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module_exit(spmi_pmic_arb_debug_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:spmi_pmic_arb_debug");
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