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KVM: x86: Widen x86_exception's error_code to 64 bits

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Widen the error_code field in struct x86_exception from u16 to u64 to
accommodate AMD's NPF error code, which defines information bits above
bit 31, e.g. PFERR_GUEST_FINAL_MASK (bit 32), and PFERR_GUEST_PAGE_MASK
(bit 33).

Retain the u16 type for the local errcode variable in walk_addr_generic
as the walker synthesizes conventional #PF error codes that are
architecturally limited to bits 15:0.

Signed-off-by: Kevin Cheng <chengkev@google.com>
Link: https://patch.msgid.link/20260522232701.3671446-2-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
This commit is contained in:
Kevin Cheng 2026-05-22 16:26:57 -07:00 committed by Sean Christopherson
parent 66472e8670
commit bb24edbb67
2 changed files with 7 additions and 1 deletions
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2
arch/x86/kvm/kvm_emulate.h
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@ -22,7 +22,7 @@ enum x86_intercept_stage;
struct x86_exception {
u8 vector;
bool error_code_valid;
u16 error_code;
u64 error_code;
bool nested_page_fault;
union {
u64 address; /* cr2 or nested page fault gpa */

6
arch/x86/kvm/mmu/paging_tmpl.h
View File

@ -328,6 +328,12 @@ static int FNAME(walk_addr_generic)(struct guest_walker *walker,
const int write_fault = access & PFERR_WRITE_MASK;
const int user_fault = access & PFERR_USER_MASK;
const int fetch_fault = access & PFERR_FETCH_MASK;
/*
* Note! Track the error_code that's common to legacy shadow paging
* and NPT shadow paging as a u16 to guard against unintentionally
* setting any of bits 63:16. Architecturally, the #PF error code is
* 32 bits, and Intel CPUs don't support settings bits 31:16.
*/
u16 errcode = 0;
gpa_t real_gpa;
gfn_t gfn;