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drm/xe/xe_sysctrl: Add System Controller types and device integration

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Add foundational type definitions for System Controller (sysctrl) support
and integrate them into the xe_device structure. Introduce a capability
flag in device descriptor and runtime information to record sysctrl
presence on supported platforms.

System Controller is a separate firmware-managed entity responsible for
selected platform-level control and coordination tasks on Intel Xe3p
discrete GPU platforms. The driver communicates with it via a mailbox
interface for delegated operations.

This commit introduces core data structures required for sysctrl support,
including MMIO region definitions, a command mutex, and state tracking
required for mailbox communication.

No functional changes. This patch provides preparatory infrastructure
for System Controller support.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patch.msgid.link/20260327131837.2192929-10-anoop.c.vijay@intel.com
This commit is contained in:
Anoop Vijay 2026-03-27 06:18:38 -07:00 committed by Umesh Nerlige Ramappa
parent df03d7c2bb
commit bb2447ef6a
3 changed files with 39 additions and 0 deletions
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6
drivers/gpu/drm/xe/xe_device_types.h
View File

@ -27,6 +27,7 @@
#include "xe_sriov_vf_ccs_types.h"
#include "xe_step_types.h"
#include "xe_survivability_mode_types.h"
#include "xe_sysctrl_types.h"
#include "xe_tile_types.h"
#include "xe_validation.h"
@ -196,6 +197,8 @@ struct xe_device {
u8 has_soc_remapper_telem:1;
/** @info.has_sriov: Supports SR-IOV */
u8 has_sriov:1;
/** @info.has_sysctrl: Supports System Controller */
u8 has_sysctrl:1;
/** @info.has_usm: Device has unified shared memory support */
u8 has_usm:1;
/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
@ -508,6 +511,9 @@ struct xe_device {
/** @i2c: I2C host controller */
struct xe_i2c *i2c;
/** @sc: System Controller */
struct xe_sysctrl sc;
/** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */
u32 atomic_svm_timeslice_ms;

1
drivers/gpu/drm/xe/xe_pci_types.h
View File

@ -57,6 +57,7 @@ struct xe_device_desc {
u8 has_soc_remapper_sysctrl:1;
u8 has_soc_remapper_telem:1;
u8 has_sriov:1;
u8 has_sysctrl:1;
u8 needs_scratch:1;
u8 skip_guc_pc:1;
u8 skip_mtcfg:1;

32
drivers/gpu/drm/xe/xe_sysctrl_types.h Normal file
View File

@ -0,0 +1,32 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2026 Intel Corporation
*/
#ifndef _XE_SYSCTRL_TYPES_H_
#define _XE_SYSCTRL_TYPES_H_
#include <linux/mutex.h>
#include <linux/types.h>
struct xe_mmio;
/**
* struct xe_sysctrl - System Controller driver context
*
* This structure maintains the runtime state for System Controller
* communication. All fields are initialized during xe_sysctrl_init()
* and protected appropriately for concurrent access.
*/
struct xe_sysctrl {
/** @mmio: MMIO region for system control registers */
struct xe_mmio *mmio;
/** @cmd_lock: Mutex protecting mailbox command operations */
struct mutex cmd_lock;
/** @phase_bit: Message boundary phase toggle bit (0 or 1) */
bool phase_bit;
};
#endif