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wifi: rtw89: 8852b: refine hardware parameters for RFE type 5

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The RFE type 5 should set different DSWR parameters when card power on.
Therefore, add the corresponding register settings for this type.

Signed-off-by: Dian-Syuan Yang <dian_syuan0116@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20251231090647.56407-12-pkshih@realtek.com
This commit is contained in:
Dian-Syuan Yang 2025-12-31 17:06:47 +08:00 committed by Ping-Ke Shih
parent eb57be32f4
commit baef3d5d96
2 changed files with 24 additions and 2 deletions
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2
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -323,7 +323,9 @@
#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
#define R_AX_SPS_DIG_OFF_CTRL0 0x0400
#define B_AX_R1_L1_MASK GENMASK(7, 6)
#define B_AX_C3_L1_MASK GENMASK(5, 4)
#define B_AX_C2_L1_MASK GENMASK(3, 2)
#define B_AX_C1_L1_MASK GENMASK(1, 0)
#define R_AX_AFE_OFF_CTRL1 0x0444

24
drivers/net/wireless/realtek/rtw89/rtw8852b.c
View File

@ -313,6 +313,27 @@ static void rtw8852b_pwr_sps_ana(struct rtw89_dev *rtwdev)
rtw89_write16(rtwdev, R_AX_SPS_ANA_ON_CTRL2, RTL8852B_RFE_05_SPS_ANA);
}
static void rtw8852b_pwr_sps_dig_off(struct rtw89_dev *rtwdev)
{
struct rtw89_efuse *efuse = &rtwdev->efuse;
if (efuse->rfe_type == 0x5) {
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
B_AX_C1_L1_MASK, 0x1);
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
B_AX_C2_L1_MASK, 0x1);
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
B_AX_C3_L1_MASK, 0x2);
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
B_AX_R1_L1_MASK, 0x1);
} else {
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
B_AX_C1_L1_MASK, 0x1);
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
B_AX_C3_L1_MASK, 0x3);
}
}
static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
{
u32 val32;
@ -338,8 +359,7 @@ static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
if (ret)
return ret;
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
rtw8852b_pwr_sps_dig_off(rtwdev);
rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);