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regmap-i2c: add SMBus byte/word reg16 bus for adapters lacking I2C_FUNC_I2C
AMD PIIX4 SMBus adapters, present on AMD SP5/EPYC-based platforms
(including Cisco 8000 series routers), support SMBUS_BYTE_DATA and
SMBUS_WORD_DATA but lack I2C_FUNC_I2C and I2C_FUNC_SMBUS_I2C_BLOCK.
When at24 (or any driver) requests a regmap with reg_bits=16 and
val_bits=8 on such an adapter, regmap_get_i2c_bus() finds no matching
bus and returns -ENOTSUPP. The existing regmap_i2c_smbus_i2c_block_reg16
bus type already implements 16-bit addressed reads using only
write_byte_data() + read_byte() primitives, but its selection is gated
on I2C_FUNC_SMBUS_I2C_BLOCK which these adapters lack.
Add a new regmap_smbus_byte_word_reg16 bus that:
READ: reuses regmap_i2c_smbus_i2c_read_reg16() -- sets the 16-bit
address via write_byte_data(addr_lo, addr_hi), then reads
bytes sequentially via read_byte() (EEPROM auto-increments).
Requires only SMBUS_BYTE_DATA.
WRITE: uses write_word_data(addr_hi, (data << 8) | addr_lo) to
encode one data byte per SMBus WORD transaction.
Requires only SMBUS_WORD_DATA. Single-byte writes only.
The new bus is selected in regmap_get_i2c_bus() when reg_bits=16,
val_bits=8, and the adapter has SMBUS_BYTE_DATA | SMBUS_WORD_DATA but
not I2C_FUNC_I2C or SMBUS_I2C_BLOCK. The branch is placed after the
existing I2C_BLOCK_reg16 check so adapters with full block support
continue to use the faster path.
This fixes at24 EEPROM probe failures on PIIX4:
at24 3-0055: probe with driver at24 failed with error -524
No driver changes are required -- at24 already passes reg_bits=16 to
devm_regmap_init_i2c(), which now succeeds.
Signed-off-by: Nishanth Sampath Kumar <nissampa@cisco.com>
Link: https://patch.msgid.link/20260407233927.498932-1-nissampa@cisco.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
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@ -303,6 +303,50 @@ static const struct regmap_bus regmap_i2c_smbus_i2c_block_reg16 = {
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.max_raw_write = I2C_SMBUS_BLOCK_MAX - 2,
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};
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/*
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* SMBus byte/word reg16 support for adapters that have SMBUS_BYTE_DATA
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* and SMBUS_WORD_DATA but lack I2C_FUNC_I2C and I2C_FUNC_SMBUS_I2C_BLOCK,
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* such as the AMD PIIX4.
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*
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* READ: set 16-bit EEPROM address via write_byte_data(addr_lo, addr_hi),
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* then sequentially read bytes via read_byte() (EEPROM auto-
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* increments the address pointer). Same as the I2C-block reg16
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* read path above.
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*
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* WRITE: encode the low address byte and data into a word transaction:
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* write_word_data(addr_hi, (data_byte << 8) | addr_lo).
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* Only single-byte writes are supported (one value per transaction).
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*/
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static int regmap_smbus_word_write_reg16(void *context, const void *data,
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size_t count)
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{
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struct device *dev = context;
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struct i2c_client *i2c = to_i2c_client(dev);
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u8 addr_hi, addr_lo, val;
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/*
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* data layout: [addr_hi, addr_lo, val0, val1, ...].
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* Only single-byte value writes are supported; multi-byte would
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* require raw I2C (or repeated word writes with incrementing address).
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*/
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if (count != 3)
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return -EINVAL;
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addr_hi = ((u8 *)data)[0];
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addr_lo = ((u8 *)data)[1];
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val = ((u8 *)data)[2];
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return i2c_smbus_write_word_data(i2c, addr_hi,
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cpu_to_le16(((u16)val << 8) | addr_lo));
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}
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static const struct regmap_bus regmap_smbus_byte_word_reg16 = {
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.write = regmap_smbus_word_write_reg16,
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.read = regmap_i2c_smbus_i2c_read_reg16,
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.max_raw_read = I2C_SMBUS_BLOCK_MAX - 2,
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.max_raw_write = 1,
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};
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static const struct regmap_bus *regmap_get_i2c_bus(struct i2c_client *i2c,
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const struct regmap_config *config)
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{
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@ -321,6 +365,11 @@ static const struct regmap_bus *regmap_get_i2c_bus(struct i2c_client *i2c,
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i2c_check_functionality(i2c->adapter,
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I2C_FUNC_SMBUS_I2C_BLOCK))
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bus = ®map_i2c_smbus_i2c_block_reg16;
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else if (config->val_bits == 8 && config->reg_bits == 16 &&
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i2c_check_functionality(i2c->adapter,
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I2C_FUNC_SMBUS_BYTE_DATA |
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I2C_FUNC_SMBUS_WORD_DATA))
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bus = ®map_smbus_byte_word_reg16;
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else if (config->val_bits == 16 && config->reg_bits == 8 &&
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i2c_check_functionality(i2c->adapter,
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I2C_FUNC_SMBUS_WORD_DATA))
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