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arm64: dts: renesas: r9a08g046: Add RSPI{0..2} nodes

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Add device tree nodes for the three RSPI channels on the RZ/G3L
(R9A08G046) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260529130704.327505-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2026-05-29 14:07:00 +01:00 committed by Geert Uytterhoeven
parent 4fb32d9e48
commit ba82a7f75e
1 changed files with 69 additions and 0 deletions
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69
arch/arm64/boot/dts/renesas/r9a08g046.dtsi
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@ -358,6 +358,75 @@ i2c3: i2c@10090c00 {
status = "disabled";
};
rspi0: spi@100b0000 {
compatible = "renesas,r9a08g046-rspi";
reg = <0 0x100b0000 0 0x1000>;
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 444 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD R9A08G046_RSPI0_PCLK>,
<&cpg CPG_MOD R9A08G046_RSPI0_TCLK>;
clock-names = "pclk", "tclk";
resets = <&cpg R9A08G046_RSPI0_PRESETN>,
<&cpg R9A08G046_RSPI0_TRESETN>;
reset-names = "presetn", "tresetn";
dmas = <&dmac 0x26f2>, <&dmac 0x26f1>;
dma-names = "rx", "tx";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rspi1: spi@100e9000 {
compatible = "renesas,r9a08g046-rspi";
reg = <0 0x100e9000 0 0x1000>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 447 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD R9A08G046_RSPI1_PCLK>,
<&cpg CPG_MOD R9A08G046_RSPI1_TCLK>;
clock-names = "pclk", "tclk";
resets = <&cpg R9A08G046_RSPI1_PRESETN>,
<&cpg R9A08G046_RSPI1_TRESETN>;
reset-names = "presetn", "tresetn";
dmas = <&dmac 0x26f6>, <&dmac 0x26f5>;
dma-names = "rx", "tx";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rspi2: spi@100ea000 {
compatible = "renesas,r9a08g046-rspi";
reg = <0 0x100ea000 0 0x1000>;
interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 454 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD R9A08G046_RSPI2_PCLK>,
<&cpg CPG_MOD R9A08G046_RSPI2_TCLK>;
clock-names = "pclk", "tclk";
resets = <&cpg R9A08G046_RSPI2_PRESETN>,
<&cpg R9A08G046_RSPI2_TRESETN>;
reset-names = "presetn", "tresetn";
dmas = <&dmac 0x26fa>, <&dmac 0x26f9>;
dma-names = "rx", "tx";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rsci0: serial@100b8000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100b8000 0 0x1000>;