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net/mlx5: Drop MR cache related code
Following mlx5_ib move to using FRMR pools, drop all unused code of MR cache. Signed-off-by: Michael Guralnik <michaelgur@nvidia.com> Reviewed-by: Yishai Hadas <yishaih@nvidia.com> Signed-off-by: Edward Srouji <edwards@nvidia.com> Link: https://patch.msgid.link/20260226-frmr_pools-v4-7-95360b54f15e@nvidia.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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@ -110,74 +110,9 @@ static struct mlx5_profile profile[] = {
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},
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[2] = {
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.mask = MLX5_PROF_MASK_QP_SIZE |
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MLX5_PROF_MASK_MR_CACHE,
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.mask = MLX5_PROF_MASK_QP_SIZE,
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.log_max_qp = LOG_MAX_SUPPORTED_QPS,
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.num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
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.mr_cache[0] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[1] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[2] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[3] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[4] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[5] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[6] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[7] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[8] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[9] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[10] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[11] = {
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.size = 500,
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.limit = 250
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},
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.mr_cache[12] = {
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.size = 64,
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.limit = 32
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},
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.mr_cache[13] = {
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.size = 32,
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.limit = 16
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},
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.mr_cache[14] = {
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.size = 16,
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.limit = 8
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},
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.mr_cache[15] = {
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.size = 8,
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.limit = 4
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},
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},
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[3] = {
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.mask = MLX5_PROF_MASK_QP_SIZE,
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@ -705,23 +705,12 @@ struct mlx5_st;
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enum {
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MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
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MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
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};
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enum {
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MKEY_CACHE_LAST_STD_ENTRY = 20,
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MLX5_IMR_KSM_CACHE_ENTRY,
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MAX_MKEY_CACHE_ENTRIES
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};
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struct mlx5_profile {
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u64 mask;
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u8 log_max_qp;
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u8 num_cmd_caches;
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struct {
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int size;
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int limit;
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} mr_cache[MAX_MKEY_CACHE_ENTRIES];
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};
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struct mlx5_hca_cap {
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