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EDAC/{skx_common,i10nm}: Refactor enable_retry_rd_err_log()
Refactor enable_retry_rd_err_log() using helper functions for both DDR and HBM, making the RRL control bits configurable instead of hard-coded. Additionally, explicitly define the four RRL modes for better readability. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Feng Xu <feng.f.xu@intel.com> Link: https://lore.kernel.org/r/20250417150724.1170168-6-qiuxu.zhuo@intel.com
This commit is contained in:
Qiuxu Zhuo
Tony Luck
parent
1a8a6af663
commit
ba3985c1fa
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@ -72,11 +72,6 @@
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#define I10NM_SAD_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
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#define I10NM_SAD_NM_CACHEABLE(reg) GET_BITFIELD(reg, 5, 5)
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#define RETRY_RD_ERR_LOG_UC BIT(1)
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#define RETRY_RD_ERR_LOG_EN_PATSPR BIT(13)
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#define RETRY_RD_ERR_LOG_NOOVER BIT(14)
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#define RETRY_RD_ERR_LOG_EN BIT(15)
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#define RETRY_RD_ERR_LOG_NOOVER_UC (BIT(14) | BIT(1))
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#define RETRY_RD_ERR_LOG_OVER_UC_V (BIT(2) | BIT(1) | BIT(0))
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static struct list_head *i10nm_edac_list;
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@ -88,153 +83,193 @@ static bool mem_cfg_2lm;
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static struct reg_rrl icx_reg_rrl_ddr = {
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.set_num = 2,
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.modes = {LRE_SCRUB, LRE_DEMAND},
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.offsets = {
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{0x22c60, 0x22c54, 0x22c5c, 0x22c58, 0x22c28, 0x20ed8},
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{0x22e54, 0x22e60, 0x22e64, 0x22e58, 0x22e5c, 0x20ee0},
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},
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.widths = {4, 4, 4, 4, 4, 8},
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.uc_mask = BIT(1),
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.en_patspr_mask = BIT(13),
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.noover_mask = BIT(14),
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.en_mask = BIT(15),
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};
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static struct reg_rrl spr_reg_rrl_ddr = {
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.set_num = 3,
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.modes = {LRE_SCRUB, LRE_DEMAND, FRE_DEMAND},
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.offsets = {
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{0x22c60, 0x22c54, 0x22f08, 0x22c58, 0x22c28, 0x20ed8},
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{0x22e54, 0x22e60, 0x22f10, 0x22e58, 0x22e5c, 0x20ee0},
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{0x22c70, 0x22d80, 0x22f18, 0x22d58, 0x22c64, 0x20f10},
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},
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.widths = {4, 4, 8, 4, 4, 8},
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.uc_mask = BIT(1),
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.en_patspr_mask = BIT(13),
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.noover_mask = BIT(14),
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.en_mask = BIT(15),
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};
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static struct reg_rrl spr_reg_rrl_hbm_pch0 = {
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.set_num = 2,
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.modes = {LRE_SCRUB, LRE_DEMAND},
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.offsets = {
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{0x2860, 0x2854, 0x2b08, 0x2858, 0x2828, 0x0ed8},
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{0x2a54, 0x2a60, 0x2b10, 0x2a58, 0x2a5c, 0x0ee0},
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},
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.widths = {4, 4, 8, 4, 4, 8},
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.uc_mask = BIT(1),
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.en_patspr_mask = BIT(13),
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.noover_mask = BIT(14),
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.en_mask = BIT(15),
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};
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static struct reg_rrl spr_reg_rrl_hbm_pch1 = {
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.set_num = 2,
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.modes = {LRE_SCRUB, LRE_DEMAND},
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.offsets = {
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{0x2c60, 0x2c54, 0x2f08, 0x2c58, 0x2c28, 0x0fa8},
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{0x2e54, 0x2e60, 0x2f10, 0x2e58, 0x2e5c, 0x0fb0},
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},
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.widths = {4, 4, 8, 4, 4, 8},
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.uc_mask = BIT(1),
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.en_patspr_mask = BIT(13),
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.noover_mask = BIT(14),
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.en_mask = BIT(15),
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};
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static void __enable_retry_rd_err_log(struct skx_imc *imc, int chan, bool enable, u32 *rrl_ctl,
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u32 *offsets_scrub, u32 *offsets_demand,
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u32 *offsets_demand2)
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static u64 read_imc_reg(struct skx_imc *imc, int chan, u32 offset, u8 width)
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{
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u32 s, d, d2;
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switch (width) {
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case 4:
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return I10NM_GET_REG32(imc, chan, offset);
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case 8:
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return I10NM_GET_REG64(imc, chan, offset);
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default:
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i10nm_printk(KERN_ERR, "Invalid readd RRL 0x%x width %d\n", offset, width);
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return 0;
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}
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}
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s = I10NM_GET_REG32(imc, chan, offsets_scrub[0]);
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d = I10NM_GET_REG32(imc, chan, offsets_demand[0]);
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if (offsets_demand2)
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d2 = I10NM_GET_REG32(imc, chan, offsets_demand2[0]);
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static void write_imc_reg(struct skx_imc *imc, int chan, u32 offset, u8 width, u64 val)
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{
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switch (width) {
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case 4:
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return I10NM_SET_REG32(imc, chan, offset, (u32)val);
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default:
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i10nm_printk(KERN_ERR, "Invalid write RRL 0x%x width %d\n", offset, width);
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}
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}
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static void enable_rrl(struct skx_imc *imc, int chan, struct reg_rrl *rrl,
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int rrl_set, bool enable, u32 *rrl_ctl)
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{
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enum rrl_mode mode = rrl->modes[rrl_set];
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u32 offset = rrl->offsets[rrl_set][0], v;
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u8 width = rrl->widths[0];
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bool first, scrub;
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/* First or last read error. */
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first = (mode == FRE_SCRUB || mode == FRE_DEMAND);
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/* Patrol scrub or on-demand read error. */
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scrub = (mode == FRE_SCRUB || mode == LRE_SCRUB);
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v = read_imc_reg(imc, chan, offset, width);
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if (enable) {
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/* Save default configurations */
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rrl_ctl[0] = s;
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rrl_ctl[1] = d;
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if (offsets_demand2)
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rrl_ctl[2] = d2;
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/* Save default configurations. */
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*rrl_ctl = v;
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v &= ~rrl->uc_mask;
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s &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
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s |= RETRY_RD_ERR_LOG_EN_PATSPR;
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s |= RETRY_RD_ERR_LOG_EN;
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d &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
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d &= ~RETRY_RD_ERR_LOG_EN_PATSPR;
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d |= RETRY_RD_ERR_LOG_EN;
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if (first)
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v |= rrl->noover_mask;
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else
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v &= ~rrl->noover_mask;
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if (offsets_demand2) {
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d2 &= ~RETRY_RD_ERR_LOG_UC;
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d2 &= ~RETRY_RD_ERR_LOG_EN_PATSPR;
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d2 |= RETRY_RD_ERR_LOG_NOOVER;
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d2 |= RETRY_RD_ERR_LOG_EN;
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}
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if (scrub)
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v |= rrl->en_patspr_mask;
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else
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v &= ~rrl->en_patspr_mask;
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v |= rrl->en_mask;
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} else {
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/* Restore default configurations */
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if (rrl_ctl[0] & RETRY_RD_ERR_LOG_UC)
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s |= RETRY_RD_ERR_LOG_UC;
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if (rrl_ctl[0] & RETRY_RD_ERR_LOG_NOOVER)
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s |= RETRY_RD_ERR_LOG_NOOVER;
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if (!(rrl_ctl[0] & RETRY_RD_ERR_LOG_EN_PATSPR))
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s &= ~RETRY_RD_ERR_LOG_EN_PATSPR;
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if (!(rrl_ctl[0] & RETRY_RD_ERR_LOG_EN))
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s &= ~RETRY_RD_ERR_LOG_EN;
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if (rrl_ctl[1] & RETRY_RD_ERR_LOG_UC)
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d |= RETRY_RD_ERR_LOG_UC;
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if (rrl_ctl[1] & RETRY_RD_ERR_LOG_NOOVER)
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d |= RETRY_RD_ERR_LOG_NOOVER;
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if (rrl_ctl[1] & RETRY_RD_ERR_LOG_EN_PATSPR)
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d |= RETRY_RD_ERR_LOG_EN_PATSPR;
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if (!(rrl_ctl[1] & RETRY_RD_ERR_LOG_EN))
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d &= ~RETRY_RD_ERR_LOG_EN;
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/* Restore default configurations. */
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if (*rrl_ctl & rrl->uc_mask)
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v |= rrl->uc_mask;
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if (offsets_demand2) {
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if (rrl_ctl[2] & RETRY_RD_ERR_LOG_UC)
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d2 |= RETRY_RD_ERR_LOG_UC;
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if (rrl_ctl[2] & RETRY_RD_ERR_LOG_EN_PATSPR)
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d2 |= RETRY_RD_ERR_LOG_EN_PATSPR;
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if (!(rrl_ctl[2] & RETRY_RD_ERR_LOG_NOOVER))
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d2 &= ~RETRY_RD_ERR_LOG_NOOVER;
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if (!(rrl_ctl[2] & RETRY_RD_ERR_LOG_EN))
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d2 &= ~RETRY_RD_ERR_LOG_EN;
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if (first) {
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if (!(*rrl_ctl & rrl->noover_mask))
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v &= ~rrl->noover_mask;
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} else {
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if (*rrl_ctl & rrl->noover_mask)
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v |= rrl->noover_mask;
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}
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if (scrub) {
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if (!(*rrl_ctl & rrl->en_patspr_mask))
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v &= ~rrl->en_patspr_mask;
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} else {
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if (*rrl_ctl & rrl->en_patspr_mask)
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v |= rrl->en_patspr_mask;
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}
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if (!(*rrl_ctl & rrl->en_mask))
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v &= ~rrl->en_mask;
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}
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I10NM_SET_REG32(imc, chan, offsets_scrub[0], s);
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I10NM_SET_REG32(imc, chan, offsets_demand[0], d);
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if (offsets_demand2)
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I10NM_SET_REG32(imc, chan, offsets_demand2[0], d2);
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write_imc_reg(imc, chan, offset, width, v);
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}
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static void enable_rrls(struct skx_imc *imc, int chan, struct reg_rrl *rrl,
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bool enable, u32 *rrl_ctl)
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{
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for (int i = 0; i < rrl->set_num; i++)
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enable_rrl(imc, chan, rrl, i, enable, rrl_ctl + i);
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}
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static void enable_rrls_ddr(struct skx_imc *imc, bool enable)
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{
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struct reg_rrl *rrl_ddr = res_cfg->reg_rrl_ddr;
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int i, chan_num = res_cfg->ddr_chan_num;
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struct skx_channel *chan = imc->chan;
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if (!imc->mbase)
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return;
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for (i = 0; i < chan_num; i++)
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enable_rrls(imc, i, rrl_ddr, enable, chan[i].rrl_ctl[0]);
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}
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static void enable_rrls_hbm(struct skx_imc *imc, bool enable)
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{
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struct reg_rrl **rrl_hbm = res_cfg->reg_rrl_hbm;
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int i, chan_num = res_cfg->hbm_chan_num;
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struct skx_channel *chan = imc->chan;
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if (!imc->mbase || !imc->hbm_mc || !rrl_hbm[0] || !rrl_hbm[1])
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return;
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for (i = 0; i < chan_num; i++) {
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enable_rrls(imc, i, rrl_hbm[0], enable, chan[i].rrl_ctl[0]);
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enable_rrls(imc, i, rrl_hbm[1], enable, chan[i].rrl_ctl[1]);
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}
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}
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static void enable_retry_rd_err_log(bool enable)
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{
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int i, j, imc_num, chan_num;
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struct skx_channel *chan;
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struct skx_imc *imc;
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struct skx_dev *d;
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int i, imc_num;
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edac_dbg(2, "\n");
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list_for_each_entry(d, i10nm_edac_list, list) {
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imc_num = res_cfg->ddr_imc_num;
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chan_num = res_cfg->ddr_chan_num;
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for (i = 0; i < imc_num; i++) {
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imc = &d->imc[i];
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if (!imc->mbase)
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continue;
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chan = d->imc[i].chan;
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for (j = 0; j < chan_num; j++)
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__enable_retry_rd_err_log(imc, j, enable, chan[j].rrl_ctl[0],
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res_cfg->reg_rrl_ddr->offsets[0],
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res_cfg->reg_rrl_ddr->offsets[1],
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res_cfg->reg_rrl_ddr->set_num > 2 ?
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res_cfg->reg_rrl_ddr->offsets[2] : NULL);
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}
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for (i = 0; i < imc_num; i++)
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enable_rrls_ddr(&d->imc[i], enable);
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imc_num += res_cfg->hbm_imc_num;
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chan_num = res_cfg->hbm_chan_num;
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for (; i < imc_num; i++) {
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imc = &d->imc[i];
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if (!imc->mbase || !imc->hbm_mc)
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continue;
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chan = d->imc[i].chan;
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for (j = 0; j < chan_num; j++) {
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__enable_retry_rd_err_log(imc, j, enable, chan[j].rrl_ctl[0],
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res_cfg->reg_rrl_hbm[0]->offsets[0],
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res_cfg->reg_rrl_hbm[0]->offsets[1],
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NULL);
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__enable_retry_rd_err_log(imc, j, enable, chan[j].rrl_ctl[1],
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res_cfg->reg_rrl_hbm[1]->offsets[0],
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res_cfg->reg_rrl_hbm[1]->offsets[1],
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NULL);
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}
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}
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for (; i < imc_num; i++)
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enable_rrls_hbm(&d->imc[i], enable);
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}
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}
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@ -84,11 +84,31 @@
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/* Max RRL registers per set. */
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#define NUM_RRL_REG 6
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/* Modes of RRL register set. */
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enum rrl_mode {
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/* Last read error from patrol scrub. */
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LRE_SCRUB,
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/* Last read error from demand. */
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LRE_DEMAND,
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/* First read error from patrol scrub. */
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FRE_SCRUB,
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/* First read error from demand. */
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FRE_DEMAND,
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};
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/* RRL registers per {,sub-,pseudo-}channel. */
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struct reg_rrl {
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/* RRL register parts. */
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int set_num;
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enum rrl_mode modes[NUM_RRL_SET];
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u32 offsets[NUM_RRL_SET][NUM_RRL_REG];
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/* RRL register widths in byte per set. */
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u8 widths[NUM_RRL_REG];
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/* RRL control bits of the first register per set. */
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u32 uc_mask;
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u32 en_patspr_mask;
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u32 noover_mask;
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u32 en_mask;
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};
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/*
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