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drm/i915/reg: convert DP_TP_CTL/DP_TP_STATUS to REG_BIT() and friends

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Use the modern style for defining register contents. Expand the status
register contents a bit.

TODO: There are more VC payload mapping fields, spanning more registers,
and have more bits on more recent platforms.

v2:
- Fix DP_TP_STATUS_STREAMS_ENABLED_MASK mask (Imre)
- Drop status VC3 payload mapping for now

Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1ef15e6bb58ca847f89c9b39cbc9771cb57db408.1732106557.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2024-11-20 14:43:14 +02:00
parent 1cfc6f811b
commit b9b82a4796
1 changed files with 29 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
drivers/gpu/drm/i915/i915_reg.h
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@ -3823,25 +3823,26 @@ enum skl_power_gate {
#define _TGL_DP_TP_CTL_A 0x60540
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
#define DP_TP_CTL_ENABLE (1 << 31)
#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST (0 << 27)
#define DP_TP_CTL_MODE_MST (1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19)
#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19)
#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19)
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
#define DP_TP_CTL_ENABLE REG_BIT(31)
#define DP_TP_CTL_FEC_ENABLE REG_BIT(30)
#define DP_TP_CTL_MODE_MASK REG_BIT(27)
#define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0)
#define DP_TP_CTL_MODE_MST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1)
#define DP_TP_CTL_FORCE_ACT REG_BIT(25)
#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20, 19)
#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0)
#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1)
#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2)
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18)
#define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15)
#define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8)
#define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)
#define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1)
#define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4)
#define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5)
#define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2)
#define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3)
#define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7)
/* DisplayPort Transport Status */
#define _DP_TP_STATUS_A 0x64044
@ -3849,14 +3850,15 @@ enum skl_power_gate {
#define _TGL_DP_TP_STATUS_A 0x60544
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE (1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
#define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28)
#define DP_TP_STATUS_IDLE_DONE REG_BIT(25)
#define DP_TP_STATUS_ACT_SENT REG_BIT(24)
#define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23)
#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18, 16) /* 17:16 on hsw but bit 18 mbz */
#define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12)
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9, 8)
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK REG_GENMASK(5, 4)
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0)
/* DDI Buffer Control */
#define _DDI_BUF_CTL_A 0x64000