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More Qualcomm Arm64 DeviceTree fixes for v7.0
The shuffling of reset and wake GPIO properties across various Hamoa devices left things in an incomplete state, fix this. Add the missing "ranges" property to the QCM2290 MDSS DeviceTree binding example, to fix the validation warning that was introduced by the previous fix. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmnMNBkACgkQCx85Pw2Z rcV7Ew/9HTWGi/VEdxQ74WwKjmKTVNZ1zN78VpIE4LO/5HBUyNCCCxHMLRmzSptM nopqcA9wdUTBSJBhBjCPLNmkowCsyKqoa8Wd8fIdzv/quNXOYHzVFUfKLRzfB2De WZoz3sJAgoNqObqh/6A+YZ+bem7mAHy0+U5FuJnenyNJObrVJTJRlHileo4y6ufp 3gqlP9znSloZA8Szn9i1yN3VGcmrafAioMFw4wWvIfrkplJMVY8pyM6MiMSLivja 34XoxiD3OaDzjfcmZ8xLE0Sy4VB0Cj0i5YlFH+aCy+xmQEAQJnp2Yb55GYTZs/Am Mvln825GlKuMX4TK18RUFppPPTqJf6IVUANOGgx5CgDlThq3PX/qNpouRKkpTqr7 NJG1xB0DpDKGglx1Yl7quR/zvWi5MxGUDpWgGDMjrlcvvlImLHKNocpSlQRf64w/ 36Mxa9kzFuxAgH+XJ6bNK+kewYyV4Ec4FR59G8SukyEgqCz66B/G18wI4qKHF4HU XhbB9cOzQhNkrcKd76QcDx0gNWknLgpK1sENqK+OL9LZpzDtAp7/Il/+tV12LogK 4aVkwBLx2w2Vc8Z45MvQADcs0UIILNeTIwduzogVQogcJi7vCxSKglDFGMUnUzxu X7LcO+hRmrwRoRFWYoQaM9GmXzrU6k8h2H4zROJfXY14vLZGhPI= =iljH -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmnNj98ACgkQmmx57+YA GNmSWhAAi0AJen2M2A/cfSXEJvHlbk+y8Wf8GR9V0ZOIc9/FmVDxovUSGJTi/0g0 aDXwj2PmaH2EJ5xnL+mow2U+gTW4NwjYz+WJNQbzZhuu6r2uPoYovVN+8NM0nYws pDw8IaD1PWKHOPcum1pLGrG7vEtQ9cGoRL8gXvP4toCWt6pu5yhi5qjqnJxGJKhw fYkiWSJOk8lTj8GoxtBrGbXoGGQdsuMqzgiL+n/xLtQezGzR9CZ6G6daSaKAgM9z ji35yJFqvQl2/qfeWvWsBbvZtMZ5uxGSYBMxiKUjsuuOu8f2wFOU64mDJLdwaSGG YJ3gdu/DGN8+6Q+iQZV5n6ARI0Qcbe94w5Wck96u14uDbeNLDgnEueYKQEzK23mz RWrLCErIckH1/cCpuaawEZ8IU3rvMrPXMKRYn96yfO+JhxFY0gpzZsR2odKuCsf+ E6FE6JWf2KI8rS6JkZyemkvkogg/tjEJKFQ8FJ1M3UY9ZlNe4iI/nC/TPZ3/Lyci 9+Q6TPPU/LMqNc57JSBLPpT+pA+bvAG9Sde7TWcNFPJKsIHHUBrfjE060VhMAdsd B4GdpB14XHZR4UVPmngvi7sYhUGA1Z+HiBuCa3GPxi6/Kozq9vVX9N+po74tsH/9 tM2g9iOYHHMv9O2hvg4tX1BXPuUW+/xcfK4FTClitoA/aNPzS/Q= =HmIq -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-fixes-for-7.0-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes More Qualcomm Arm64 DeviceTree fixes for v7.0 The shuffling of reset and wake GPIO properties across various Hamoa devices left things in an incomplete state, fix this. Add the missing "ranges" property to the QCM2290 MDSS DeviceTree binding example, to fix the validation warning that was introduced by the previous fix. * tag 'qcom-arm64-fixes-for-7.0-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: dts: qcom: hamoa: Fix incomplete Root Port property migration dt-bindings: display/msm: qcm2290-mdss: Fix missing ranges in example arm64: dts: qcom: agatti: Fix IOMMU DT properties dt-bindings: media: venus: Fix iommus property dt-bindings: display: msm: qcm2290-mdss: Fix iommus property arm64: dts: qcom: monaco: Reserve full Gunyah metadata region arm64: dts: qcom: monaco: Fix UART10 pinconf arm64: dts: qcom: qcm6490-idp: Fix WCD9370 reset GPIO polarity arm64: dts: qcom: hamoa/x1: fix idle exit latency Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
b986e98ccd
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@ -33,7 +33,7 @@ properties:
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- const: core
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iommus:
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maxItems: 2
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maxItems: 1
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interconnects:
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items:
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@ -107,8 +107,7 @@ examples:
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interconnect-names = "mdp0-mem",
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"cpu-cfg";
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iommus = <&apps_smmu 0x420 0x2>,
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<&apps_smmu 0x421 0x0>;
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iommus = <&apps_smmu 0x420 0x2>;
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ranges;
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display-controller@5e01000 {
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@ -42,7 +42,7 @@ properties:
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- const: vcodec0_bus
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iommus:
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maxItems: 5
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maxItems: 2
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interconnects:
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maxItems: 2
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@ -102,10 +102,7 @@ examples:
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memory-region = <&pil_video_mem>;
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iommus = <&apps_smmu 0x860 0x0>,
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<&apps_smmu 0x880 0x0>,
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<&apps_smmu 0x861 0x04>,
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<&apps_smmu 0x863 0x0>,
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<&apps_smmu 0x804 0xe0>;
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<&apps_smmu 0x880 0x0>;
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interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
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&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
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@ -1669,8 +1669,7 @@ gpu: gpu@5900000 {
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&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
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interconnect-names = "gfx-mem";
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iommus = <&adreno_smmu 0 1>,
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<&adreno_smmu 2 0>;
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iommus = <&adreno_smmu 0 1>;
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operating-points-v2 = <&gpu_opp_table>;
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power-domains = <&rpmpd QCM2290_VDDCX>;
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qcom,gmu = <&gmu_wrapper>;
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@ -1951,8 +1950,7 @@ mdss: display-subsystem@5e00000 {
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power-domains = <&dispcc MDSS_GDSC>;
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iommus = <&apps_smmu 0x420 0x2>,
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<&apps_smmu 0x421 0x0>;
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iommus = <&apps_smmu 0x420 0x2>;
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interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG
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&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
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<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
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@ -2436,10 +2434,7 @@ venus: video-codec@5a00000 {
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memory-region = <&pil_video_mem>;
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iommus = <&apps_smmu 0x860 0x0>,
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<&apps_smmu 0x880 0x0>,
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<&apps_smmu 0x861 0x04>,
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<&apps_smmu 0x863 0x0>,
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<&apps_smmu 0x804 0xe0>;
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<&apps_smmu 0x880 0x0>;
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interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
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&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
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@ -269,7 +269,7 @@ cluster_c4: cpu-sleep-0 {
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idle-state-name = "ret";
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arm,psci-suspend-param = <0x00000004>;
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entry-latency-us = <180>;
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exit-latency-us = <500>;
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exit-latency-us = <320>;
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min-residency-us = <600>;
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};
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};
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@ -765,6 +765,11 @@ smem_mem: smem@90900000 {
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hwlocks = <&tcsr_mutex 3>;
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};
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gunyah_md_mem: gunyah-md-region@91a80000 {
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reg = <0x0 0x91a80000 0x0 0x80000>;
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no-map;
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};
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lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
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reg = <0x0 0x93b00000 0x0 0xf00000>;
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no-map;
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@ -6414,12 +6419,12 @@ qup_uart10_cts: qup-uart10-cts-state {
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};
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qup_uart10_rts: qup-uart10-rts-state {
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pins = "gpio84";
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pins = "gpio85";
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function = "qup1_se2";
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};
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qup_uart10_tx: qup-uart10-tx-state {
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pins = "gpio85";
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pins = "gpio86";
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function = "qup1_se2";
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};
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@ -177,7 +177,7 @@ wcd9370: audio-codec-0 {
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pinctrl-0 = <&wcd_default>;
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pinctrl-names = "default";
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reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
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vdd-buck-supply = <&vreg_l17b_1p7>;
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vdd-rxtx-supply = <&vreg_l18b_1p8>;
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@ -1032,9 +1032,6 @@ &mdss_dp3_phy {
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};
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&pcie4 {
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perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie4_default>;
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pinctrl-names = "default";
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@ -1048,10 +1045,12 @@ &pcie4_phy {
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status = "okay";
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};
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&pcie6a {
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perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
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&pcie4_port0 {
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reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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};
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&pcie6a {
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vddpe-3v3-supply = <&vreg_nvme>;
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pinctrl-0 = <&pcie6a_default>;
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@ -1067,6 +1066,11 @@ &pcie6a_phy {
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status = "okay";
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};
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&pcie6a_port0 {
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reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
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};
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&pm8550_gpios {
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rtmr0_default: rtmr0-reset-n-active-state {
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pins = "gpio10";
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@ -1216,15 +1216,17 @@ &mdss_dp3_phy {
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};
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&pcie4 {
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perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie4_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pcie4_port0 {
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reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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};
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&pcie4_phy {
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vdda-phy-supply = <&vreg_l3i_0p8>;
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vdda-pll-supply = <&vreg_l3e_1p2>;
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@ -1233,9 +1235,6 @@ &pcie4_phy {
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};
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&pcie5 {
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perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
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vddpe-3v3-supply = <&vreg_wwan>;
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pinctrl-0 = <&pcie5_default>;
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@ -1251,10 +1250,12 @@ &pcie5_phy {
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status = "okay";
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};
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&pcie6a {
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perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
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&pcie5_port0 {
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reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
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};
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&pcie6a {
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vddpe-3v3-supply = <&vreg_nvme>;
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pinctrl-names = "default";
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@ -1270,6 +1271,11 @@ &pcie6a_phy {
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status = "okay";
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};
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&pcie6a_port0 {
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reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
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};
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&pm8550_gpios {
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kypd_vol_up_n: kypd-vol-up-n-state {
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pins = "gpio6";
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@ -1081,9 +1081,6 @@ &mdss_dp3_phy {
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};
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&pcie4 {
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perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie4_default>;
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pinctrl-names = "default";
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@ -1098,6 +1095,9 @@ &pcie4_phy {
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};
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&pcie4_port0 {
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reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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wifi@0 {
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compatible = "pci17cb,1107";
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reg = <0x10000 0x0 0x0 0x0 0x0>;
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@ -1115,9 +1115,6 @@ wifi@0 {
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};
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&pcie6a {
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perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
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vddpe-3v3-supply = <&vreg_nvme>;
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pinctrl-0 = <&pcie6a_default>;
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@ -1126,6 +1123,11 @@ &pcie6a {
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status = "okay";
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};
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&pcie6a_port0 {
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reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
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};
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&pcie6a_phy {
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vdda-phy-supply = <&vreg_l1d_0p8>;
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vdda-pll-supply = <&vreg_l2j_1p2>;
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@ -1065,9 +1065,6 @@ &mdss_dp3_phy {
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};
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&pcie4 {
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perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie4_default>;
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pinctrl-names = "default";
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@ -1082,6 +1079,9 @@ &pcie4_phy {
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};
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&pcie4_port0 {
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reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
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wifi@0 {
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compatible = "pci17cb,1107";
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reg = <0x10000 0x0 0x0 0x0 0x0>;
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@ -1099,9 +1099,6 @@ wifi@0 {
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};
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&pcie6a {
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perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
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vddpe-3v3-supply = <&vreg_nvme>;
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pinctrl-0 = <&pcie6a_default>;
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@ -1110,6 +1107,11 @@ &pcie6a {
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status = "okay";
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};
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&pcie6a_port0 {
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reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
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};
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&pcie6a_phy {
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vdda-phy-supply = <&vreg_l1d_0p8>;
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vdda-pll-supply = <&vreg_l2j_1p2>;
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|
|
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|
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@ -964,9 +964,6 @@ wifi@0 {
|
|||
};
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&pcie6a {
|
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perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
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vddpe-3v3-supply = <&vreg_nvme>;
|
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|
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pinctrl-0 = <&pcie6a_default>;
|
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|
|
@ -982,6 +979,11 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
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&pcie6a_port0 {
|
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reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
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wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
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};
|
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|
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&pm8550_gpios {
|
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rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
|
|
|
|||
|
|
@ -1126,9 +1126,6 @@ &mdss_dp3_phy {
|
|||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -1143,6 +1140,9 @@ &pcie4_phy {
|
|||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
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wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
|
|
|||
|
|
@ -1033,9 +1033,6 @@ &mdss_dp3_phy {
|
|||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -1050,6 +1047,9 @@ &pcie4_phy {
|
|||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
|
@ -1067,10 +1067,6 @@ wifi@0 {
|
|||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
|
|
@ -1086,6 +1082,11 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
rtmr0_default: rtmr0-reset-n-active-state {
|
||||
pins = "gpio10";
|
||||
|
|
|
|||
|
|
@ -1131,9 +1131,6 @@ &mdss_dp3_phy {
|
|||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
@ -1148,6 +1145,9 @@ &pcie4_phy {
|
|||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
|
@ -1165,9 +1165,6 @@ wifi@0 {
|
|||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vddpe-3v3-supply = <&vreg_nvme>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
|
|
@ -1183,6 +1180,11 @@ &pcie6a_phy {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_port0 {
|
||||
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pm8550_pwm {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user