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PCI/pwrctrl: tc9563: Move Integrated MAC Endpoint out of 'tc9563_pwrctrl_ports' enum
'tc9563_pwrctrl_ports' is supposed to list only the internal ports of the switch. But it currently lists the integrated MAC Endpoint as well, which is wrong. Move it to a separate 'ep_cfg' struct and also configure/parse the ports and the MAC Endpoint separately. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://patch.msgid.link/20260725-tc9563-fix-v1-6-ec4286e31331@oss.qualcomm.com
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@ -81,7 +81,6 @@ enum tc9563_pwrctrl_ports {
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TC9563_DSP1,
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TC9563_DSP2,
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TC9563_VDSP,
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TC9563_ETHERNET,
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TC9563_MAX
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};
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@ -109,6 +108,7 @@ struct tc9563_pwrctrl {
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struct pci_pwrctrl pwrctrl;
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struct regulator_bulk_data supplies[TC9563_PWRCTL_MAX_SUPPLY];
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struct tc9563_pwrctrl_cfg cfg[TC9563_MAX];
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struct tc9563_pwrctrl_cfg ep_cfg;
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struct gpio_desc *reset_gpio;
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struct i2c_adapter *adapter;
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struct i2c_client *client;
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@ -263,9 +263,31 @@ static int tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl *tc9563,
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ARRAY_SIZE(common_pwroff_seq));
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}
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static int tc9563_pwrctrl_set_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
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enum tc9563_pwrctrl_ports port,
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bool is_l1, u32 ns)
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static int tc9563_pwrctrl_set_port_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
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enum tc9563_pwrctrl_ports port,
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bool is_l1, u32 ns)
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{
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u32 units;
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int ret;
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if (ns < TC9563_L0S_L1_DELAY_UNIT_NS)
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return 0;
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/* convert to units of 256ns */
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units = ns / TC9563_L0S_L1_DELAY_UNIT_NS;
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ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_PORT_SELECT,
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BIT(port));
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if (ret)
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return ret;
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return tc9563_pwrctrl_i2c_write(tc9563->client,
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is_l1 ? TC9563_PORT_L1_DELAY : TC9563_PORT_L0S_DELAY,
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units);
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}
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static int tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
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bool is_l1, u32 ns)
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{
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u32 rd_val, units;
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int ret;
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@ -276,33 +298,20 @@ static int tc9563_pwrctrl_set_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
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/* convert to units of 256ns */
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units = ns / TC9563_L0S_L1_DELAY_UNIT_NS;
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if (port == TC9563_ETHERNET) {
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ret = tc9563_pwrctrl_i2c_read(tc9563->client,
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TC9563_EMBEDDED_ETH_DELAY,
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&rd_val);
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if (ret)
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return ret;
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if (is_l1)
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rd_val = u32_replace_bits(rd_val, units,
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TC9563_ETH_L1_DELAY_MASK);
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else
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rd_val = u32_replace_bits(rd_val, units,
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TC9563_ETH_L0S_DELAY_MASK);
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return tc9563_pwrctrl_i2c_write(tc9563->client,
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TC9563_EMBEDDED_ETH_DELAY,
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rd_val);
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}
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ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_PORT_SELECT,
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BIT(port));
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ret = tc9563_pwrctrl_i2c_read(tc9563->client, TC9563_EMBEDDED_ETH_DELAY,
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&rd_val);
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if (ret)
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return ret;
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return tc9563_pwrctrl_i2c_write(tc9563->client,
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is_l1 ? TC9563_PORT_L1_DELAY : TC9563_PORT_L0S_DELAY,
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units);
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if (is_l1)
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rd_val = u32_replace_bits(rd_val, units,
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TC9563_ETH_L1_DELAY_MASK);
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else
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rd_val = u32_replace_bits(rd_val, units,
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TC9563_ETH_L0S_DELAY_MASK);
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return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_EMBEDDED_ETH_DELAY,
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rd_val);
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}
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static int tc9563_pwrctrl_set_tx_amplitude(struct tc9563_pwrctrl *tc9563,
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@ -436,11 +445,9 @@ static int tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl *tc9563,
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return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_RESET_GPIO, val);
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}
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static int tc9563_pwrctrl_parse_device_dt(struct tc9563_pwrctrl *tc9563,
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struct device_node *node,
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enum tc9563_pwrctrl_ports port)
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static int tc9563_pwrctrl_parse_device_dt(struct device_node *node,
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struct tc9563_pwrctrl_cfg *cfg)
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{
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struct tc9563_pwrctrl_cfg *cfg = &tc9563->cfg[port];
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int ret;
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/* Disable port if the status of the port is disabled. */
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@ -511,13 +518,13 @@ static int tc9563_pwrctrl_power_on(struct pci_pwrctrl *pwrctrl)
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goto power_off;
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}
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ret = tc9563_pwrctrl_set_l0s_l1_entry_delay(tc9563, i, false, cfg->l0s_delay);
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ret = tc9563_pwrctrl_set_port_l0s_l1_entry_delay(tc9563, i, false, cfg->l0s_delay);
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if (ret) {
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dev_err(dev, "Setting L0s entry delay failed\n");
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goto power_off;
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}
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ret = tc9563_pwrctrl_set_l0s_l1_entry_delay(tc9563, i, true, cfg->l1_delay);
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ret = tc9563_pwrctrl_set_port_l0s_l1_entry_delay(tc9563, i, true, cfg->l1_delay);
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if (ret) {
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dev_err(dev, "Setting L1 entry delay failed\n");
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goto power_off;
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@ -542,6 +549,21 @@ static int tc9563_pwrctrl_power_on(struct pci_pwrctrl *pwrctrl)
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}
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}
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/* Configure the integrated Ethernet MAC endpoint */
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ret = tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(tc9563, false,
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tc9563->ep_cfg.l0s_delay);
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if (ret) {
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dev_err(dev, "Setting Ethernet L0s entry delay failed\n");
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goto power_off;
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}
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ret = tc9563_pwrctrl_set_eth_l0s_l1_entry_delay(tc9563, true,
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tc9563->ep_cfg.l1_delay);
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if (ret) {
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dev_err(dev, "Setting Ethernet L1 entry delay failed\n");
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goto power_off;
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}
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ret = tc9563_pwrctrl_assert_deassert_reset(tc9563, true);
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if (!ret)
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return 0;
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@ -599,8 +621,7 @@ static int tc9563_pwrctrl_probe(struct platform_device *pdev)
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pci_pwrctrl_init(&tc9563->pwrctrl, dev);
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port = TC9563_USP;
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ret = tc9563_pwrctrl_parse_device_dt(tc9563, node, port);
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ret = tc9563_pwrctrl_parse_device_dt(node, &tc9563->cfg[TC9563_USP]);
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if (ret) {
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dev_err(dev, "failed to parse device tree properties: %d\n", ret);
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goto remove_i2c;
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@ -611,9 +632,12 @@ static int tc9563_pwrctrl_probe(struct platform_device *pdev)
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* The first node represents DSP1, the second node represents DSP2,
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* and so on.
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*/
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port = TC9563_USP;
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for_each_child_of_node_scoped(node, child) {
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port++;
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ret = tc9563_pwrctrl_parse_device_dt(tc9563, child, port);
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if (++port >= TC9563_MAX)
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break;
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ret = tc9563_pwrctrl_parse_device_dt(child, &tc9563->cfg[port]);
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if (ret)
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break;
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@ -626,8 +650,8 @@ static int tc9563_pwrctrl_probe(struct platform_device *pdev)
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of_get_next_available_child(child, NULL);
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if (eth) {
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ret = tc9563_pwrctrl_parse_device_dt(tc9563,
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eth, TC9563_ETHERNET);
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ret = tc9563_pwrctrl_parse_device_dt(eth,
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&tc9563->ep_cfg);
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if (ret)
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break;
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}
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