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clk: qcom: gcc: Add support for Global Clock controller found on MSM8940
Modify existing MSM8917 driver to support MSM8940 SoC. MSM8940 SoC has the same changes as MSM8937 SoC, but with additional IPA clk and different GFX3D clock frequency table. Signed-off-by: Daniil Titov <daniilt971@gmail.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251117-gcc-msm8940-sdm439-v2-2-4af57c8bc7eb@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Daniil Titov
Bjorn Andersson
parent
d88d5bedb5
commit
b97a615005
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@ -387,12 +387,12 @@ config MSM_GCC_8916
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SD/eMMC, display, graphics, camera etc.
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config MSM_GCC_8917
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tristate "MSM89(17/37)/QM215 Global Clock Controller"
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tristate "MSM89(17/37/40)/QM215 Global Clock Controller"
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depends on ARM64 || COMPILE_TEST
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select QCOM_GDSC
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help
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Support for the global clock controller on msm8917, msm8937
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and qm215 devices.
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Support for the global clock controller on msm8917, msm8937,
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msm8940 and qm215 devices.
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Say Y if you want to use devices such as UART, SPI i2c, USB,
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SD/eMMC, display, graphics, camera etc.
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@ -957,6 +957,27 @@ static const struct freq_tbl ftbl_gfx3d_clk_src_msm8937[] = {
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{ }
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};
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static const struct freq_tbl ftbl_gfx3d_clk_src_msm8940[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(50000000, P_GPLL0, 16, 0, 0),
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F(80000000, P_GPLL0, 10, 0, 0),
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F(100000000, P_GPLL0, 8, 0, 0),
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F(160000000, P_GPLL0, 5, 0, 0),
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F(200000000, P_GPLL0, 4, 0, 0),
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F(216000000, P_GPLL6, 5, 0, 0),
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F(228570000, P_GPLL0, 3.5, 0, 0),
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F(240000000, P_GPLL6, 4.5, 0, 0),
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F(266670000, P_GPLL0, 3, 0, 0),
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F(300000000, P_GPLL3, 1, 0, 0),
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F(320000000, P_GPLL0, 2.5, 0, 0),
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F(375000000, P_GPLL3, 1, 0, 0),
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F(400000000, P_GPLL0, 2, 0, 0),
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F(450000000, P_GPLL3, 1, 0, 0),
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F(475000000, P_GPLL3, 1, 0, 0),
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F(500000000, P_GPLL3, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 gfx3d_clk_src = {
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.cmd_rcgr = 0x59000,
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.hid_width = 5,
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@ -3307,6 +3328,19 @@ static struct clk_branch gcc_vfe_tbu_clk = {
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}
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};
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static struct clk_branch gcc_ipa_tbu_clk = {
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.halt_reg = 0x120a0,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x4500c,
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.enable_mask = BIT(16),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_ipa_tbu_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc venus_gdsc = {
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.gdscr = 0x4c018,
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.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
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@ -3764,6 +3798,189 @@ static struct clk_regmap *gcc_msm8937_clocks[] = {
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[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
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};
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static struct clk_regmap *gcc_msm8940_clocks[] = {
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[GPLL0] = &gpll0.clkr,
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[GPLL0_EARLY] = &gpll0_early.clkr,
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[GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
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[GPLL3] = &gpll3.clkr,
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[GPLL3_EARLY] = &gpll3_early.clkr,
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[GPLL4] = &gpll4.clkr,
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[GPLL4_EARLY] = &gpll4_early.clkr,
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[GPLL6] = &gpll6,
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[GPLL6_EARLY] = &gpll6_early.clkr,
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[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
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[MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
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[MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
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[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
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[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
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[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
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[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
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[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
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[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
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[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
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[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
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[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
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[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
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[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
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[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
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[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
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[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
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[MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
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[MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
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[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
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[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
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[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
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[MSM8937_BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
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[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
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[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
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[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
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[CCI_CLK_SRC] = &cci_clk_src.clkr,
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[CPP_CLK_SRC] = &cpp_clk_src.clkr,
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[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
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[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
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[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
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[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
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[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
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[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
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[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
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[MSM8937_ESC1_CLK_SRC] = &esc1_clk_src.clkr,
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[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
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[GP1_CLK_SRC] = &gp1_clk_src.clkr,
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[GP2_CLK_SRC] = &gp2_clk_src.clkr,
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[GP3_CLK_SRC] = &gp3_clk_src.clkr,
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[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
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[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
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[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
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[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
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[MDP_CLK_SRC] = &mdp_clk_src.clkr,
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[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
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[MSM8937_PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
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[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
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[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
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[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
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[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
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[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
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[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
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[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
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[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
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[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
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[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
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[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
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[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
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[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
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[MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
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[MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
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[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
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[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
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[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
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[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
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[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
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[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
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[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
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[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
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[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
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[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
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[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
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[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
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[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
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[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
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[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
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[MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
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[MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
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[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
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[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
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[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
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[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
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[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
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[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
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[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
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[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
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[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
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[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
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[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
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[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
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[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
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[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
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[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
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[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
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[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
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[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
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[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
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[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
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[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
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[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
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[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
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[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
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[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
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[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
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[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
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[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
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[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
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[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
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[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
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[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
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[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
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[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
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[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
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[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
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[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
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[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
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[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
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[GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
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[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
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[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
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[GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
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[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
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[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
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[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
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[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
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[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
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[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
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[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
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[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
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[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
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[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
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[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
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[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
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[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
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[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
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[MSM8937_GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
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[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
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[MSM8937_GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
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[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
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[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
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[MSM8937_GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
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[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
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[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
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[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
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[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
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[MSM8937_GCC_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
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[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
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[MSM8937_GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
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[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
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[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
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[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
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[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
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[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
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[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
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[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
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[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
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[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
|
||||
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
|
||||
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
|
||||
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
|
||||
[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
|
||||
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
|
||||
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
|
||||
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
|
||||
[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
|
||||
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
|
||||
[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
|
||||
[GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
|
||||
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
|
||||
[MSM8940_GCC_IPA_TBU_CLK] = &gcc_ipa_tbu_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gcc_msm8917_resets[] = {
|
||||
[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
|
||||
[GCC_MSS_BCR] = { 0x71000 },
|
||||
|
|
@ -3834,6 +4051,16 @@ static const struct qcom_cc_desc gcc_msm8937_desc = {
|
|||
.num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc gcc_msm8940_desc = {
|
||||
.config = &gcc_msm8917_regmap_config,
|
||||
.clks = gcc_msm8940_clocks,
|
||||
.num_clks = ARRAY_SIZE(gcc_msm8940_clocks),
|
||||
.resets = gcc_msm8917_resets,
|
||||
.num_resets = ARRAY_SIZE(gcc_msm8917_resets),
|
||||
.gdscs = gcc_msm8937_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
|
||||
};
|
||||
|
||||
static void msm8937_clock_override(void)
|
||||
{
|
||||
/* GPLL3 750MHz configuration */
|
||||
|
|
@ -3871,6 +4098,9 @@ static int gcc_msm8917_probe(struct platform_device *pdev)
|
|||
} else if (gcc_desc == &gcc_msm8937_desc) {
|
||||
msm8937_clock_override();
|
||||
gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8937;
|
||||
} else if (gcc_desc == &gcc_msm8940_desc) {
|
||||
msm8937_clock_override();
|
||||
gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8940;
|
||||
}
|
||||
|
||||
regmap = qcom_cc_map(pdev, gcc_desc);
|
||||
|
|
@ -3886,6 +4116,7 @@ static const struct of_device_id gcc_msm8917_match_table[] = {
|
|||
{ .compatible = "qcom,gcc-msm8917", .data = &gcc_msm8917_desc },
|
||||
{ .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
|
||||
{ .compatible = "qcom,gcc-msm8937", .data = &gcc_msm8937_desc },
|
||||
{ .compatible = "qcom,gcc-msm8940", .data = &gcc_msm8940_desc },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gcc_msm8917_match_table);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user