drm/rockchip: csi: rk1808 dphy tx max bit rate is 2.0Gbps/lane

Change-Id: I05d35607b04b139647dc59a1725a88168a13db5b
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang 2018-10-08 11:06:05 +08:00 committed by Tao Huang
parent 5288a45056
commit b973824219

View File

@ -1248,7 +1248,7 @@ static const u32 rk1808_csi_grf_reg_fields[MAX_FIELDS] = {
static const struct rockchip_mipi_csi_plat_data rk1808_socdata = {
.csi0_grf_reg_fields = rk1808_csi_grf_reg_fields,
.max_bit_rate_per_lane = 2500000000UL,
.max_bit_rate_per_lane = 2000000000UL,
.soc_type = RK1808,
};