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media: i2c: ds90ub953: Move reg defines to a header file
Move UB953 register defines to a header file. This is done so that the deserializer driver can access the defines, and do some early serializer configuration. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Jai Luthra <jai.luthra@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Tomi Valkeinen
Hans Verkuil
parent
ca26126a6c
commit
b8e2193b1e
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@ -28,6 +28,8 @@
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#include <media/v4l2-mediabus.h>
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#include <media/v4l2-subdev.h>
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#include "ds90ub953.h"
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#define UB953_PAD_SINK 0
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#define UB953_PAD_SOURCE 1
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@ -35,93 +37,6 @@
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#define UB953_DEFAULT_CLKOUT_RATE 25000000UL
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#define UB953_REG_RESET_CTL 0x01
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#define UB953_REG_RESET_CTL_DIGITAL_RESET_1 BIT(1)
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#define UB953_REG_RESET_CTL_DIGITAL_RESET_0 BIT(0)
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#define UB953_REG_GENERAL_CFG 0x02
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#define UB953_REG_GENERAL_CFG_CONT_CLK BIT(6)
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#define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT 4
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#define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_MASK GENMASK(5, 4)
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#define UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE BIT(1)
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#define UB953_REG_GENERAL_CFG_I2C_STRAP_MODE BIT(0)
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#define UB953_REG_MODE_SEL 0x03
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#define UB953_REG_MODE_SEL_MODE_DONE BIT(3)
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#define UB953_REG_MODE_SEL_MODE_OVERRIDE BIT(4)
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#define UB953_REG_MODE_SEL_MODE_MASK GENMASK(2, 0)
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#define UB953_REG_CLKOUT_CTRL0 0x06
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#define UB953_REG_CLKOUT_CTRL1 0x07
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#define UB953_REG_I2C_CONTROL2 0x0a
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#define UB953_REG_I2C_CONTROL2_SDA_OUTPUT_SETUP_SHIFT 4
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#define UB953_REG_I2C_CONTROL2_BUS_SPEEDUP BIT(1)
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#define UB953_REG_SCL_HIGH_TIME 0x0b
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#define UB953_REG_SCL_LOW_TIME 0x0c
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#define UB953_REG_LOCAL_GPIO_DATA 0x0d
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#define UB953_REG_LOCAL_GPIO_DATA_GPIO_RMTEN(n) BIT(4 + (n))
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#define UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(n) BIT(0 + (n))
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#define UB953_REG_GPIO_INPUT_CTRL 0x0e
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#define UB953_REG_GPIO_INPUT_CTRL_OUT_EN(n) BIT(4 + (n))
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#define UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(n) BIT(0 + (n))
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#define UB953_REG_BC_CTRL 0x49
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#define UB953_REG_BC_CTRL_CRC_ERR_CLR BIT(3)
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#define UB953_REG_REV_MASK_ID 0x50
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#define UB953_REG_GENERAL_STATUS 0x52
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#define UB953_REG_GPIO_PIN_STS 0x53
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#define UB953_REG_GPIO_PIN_STS_GPIO_STS(n) BIT(0 + (n))
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#define UB953_REG_BIST_ERR_CNT 0x54
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#define UB953_REG_CRC_ERR_CNT1 0x55
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#define UB953_REG_CRC_ERR_CNT2 0x56
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#define UB953_REG_CSI_ERR_CNT 0x5c
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#define UB953_REG_CSI_ERR_STATUS 0x5d
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#define UB953_REG_CSI_ERR_DLANE01 0x5e
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#define UB953_REG_CSI_ERR_DLANE23 0x5f
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#define UB953_REG_CSI_ERR_CLK_LANE 0x60
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#define UB953_REG_CSI_PKT_HDR_VC_ID 0x61
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#define UB953_REG_PKT_HDR_WC_LSB 0x62
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#define UB953_REG_PKT_HDR_WC_MSB 0x63
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#define UB953_REG_CSI_ECC 0x64
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#define UB953_REG_IND_ACC_CTL 0xb0
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#define UB953_REG_IND_ACC_ADDR 0xb1
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#define UB953_REG_IND_ACC_DATA 0xb2
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#define UB953_REG_FPD3_RX_ID(n) (0xf0 + (n))
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#define UB953_REG_FPD3_RX_ID_LEN 6
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/* Indirect register blocks */
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#define UB953_IND_TARGET_PAT_GEN 0x00
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#define UB953_IND_TARGET_FPD3_TX 0x01
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#define UB953_IND_TARGET_DIE_ID 0x02
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#define UB953_IND_PGEN_CTL 0x01
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#define UB953_IND_PGEN_CTL_PGEN_ENABLE BIT(0)
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#define UB953_IND_PGEN_CFG 0x02
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#define UB953_IND_PGEN_CSI_DI 0x03
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#define UB953_IND_PGEN_LINE_SIZE1 0x04
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#define UB953_IND_PGEN_LINE_SIZE0 0x05
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#define UB953_IND_PGEN_BAR_SIZE1 0x06
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#define UB953_IND_PGEN_BAR_SIZE0 0x07
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#define UB953_IND_PGEN_ACT_LPF1 0x08
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#define UB953_IND_PGEN_ACT_LPF0 0x09
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#define UB953_IND_PGEN_TOT_LPF1 0x0a
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#define UB953_IND_PGEN_TOT_LPF0 0x0b
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#define UB953_IND_PGEN_LINE_PD1 0x0c
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#define UB953_IND_PGEN_LINE_PD0 0x0d
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#define UB953_IND_PGEN_VBP 0x0e
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#define UB953_IND_PGEN_VFP 0x0f
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#define UB953_IND_PGEN_COLOR(n) (0x10 + (n)) /* n <= 15 */
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/* Note: Only sync mode supported for now */
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enum ub953_mode {
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/* FPD-Link III CSI-2 synchronous mode */
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95
drivers/media/i2c/ds90ub953.h
Normal file
95
drivers/media/i2c/ds90ub953.h
Normal file
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@ -0,0 +1,95 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MEDIA_I2C_DS90UB953_H__
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#define __MEDIA_I2C_DS90UB953_H__
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#include <linux/types.h>
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#define UB953_REG_RESET_CTL 0x01
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#define UB953_REG_RESET_CTL_DIGITAL_RESET_1 BIT(1)
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#define UB953_REG_RESET_CTL_DIGITAL_RESET_0 BIT(0)
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#define UB953_REG_GENERAL_CFG 0x02
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#define UB953_REG_GENERAL_CFG_CONT_CLK BIT(6)
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#define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT 4
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#define UB953_REG_GENERAL_CFG_CSI_LANE_SEL_MASK GENMASK(5, 4)
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#define UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE BIT(1)
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#define UB953_REG_GENERAL_CFG_I2C_STRAP_MODE BIT(0)
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#define UB953_REG_MODE_SEL 0x03
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#define UB953_REG_MODE_SEL_MODE_DONE BIT(3)
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#define UB953_REG_MODE_SEL_MODE_OVERRIDE BIT(4)
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#define UB953_REG_MODE_SEL_MODE_MASK GENMASK(2, 0)
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#define UB953_REG_CLKOUT_CTRL0 0x06
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#define UB953_REG_CLKOUT_CTRL1 0x07
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#define UB953_REG_I2C_CONTROL2 0x0a
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#define UB953_REG_I2C_CONTROL2_SDA_OUTPUT_SETUP_SHIFT 4
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#define UB953_REG_I2C_CONTROL2_BUS_SPEEDUP BIT(1)
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#define UB953_REG_SCL_HIGH_TIME 0x0b
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#define UB953_REG_SCL_LOW_TIME 0x0c
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#define UB953_REG_LOCAL_GPIO_DATA 0x0d
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#define UB953_REG_LOCAL_GPIO_DATA_GPIO_RMTEN(n) BIT(4 + (n))
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#define UB953_REG_LOCAL_GPIO_DATA_GPIO_OUT_SRC(n) BIT(0 + (n))
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#define UB953_REG_GPIO_INPUT_CTRL 0x0e
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#define UB953_REG_GPIO_INPUT_CTRL_OUT_EN(n) BIT(4 + (n))
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#define UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(n) BIT(0 + (n))
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#define UB953_REG_BC_CTRL 0x49
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#define UB953_REG_BC_CTRL_CRC_ERR_CLR BIT(3)
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#define UB953_REG_REV_MASK_ID 0x50
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#define UB953_REG_GENERAL_STATUS 0x52
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#define UB953_REG_GPIO_PIN_STS 0x53
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#define UB953_REG_GPIO_PIN_STS_GPIO_STS(n) BIT(0 + (n))
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#define UB953_REG_BIST_ERR_CNT 0x54
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#define UB953_REG_CRC_ERR_CNT1 0x55
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#define UB953_REG_CRC_ERR_CNT2 0x56
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#define UB953_REG_CSI_ERR_CNT 0x5c
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#define UB953_REG_CSI_ERR_STATUS 0x5d
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#define UB953_REG_CSI_ERR_DLANE01 0x5e
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#define UB953_REG_CSI_ERR_DLANE23 0x5f
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#define UB953_REG_CSI_ERR_CLK_LANE 0x60
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#define UB953_REG_CSI_PKT_HDR_VC_ID 0x61
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#define UB953_REG_PKT_HDR_WC_LSB 0x62
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#define UB953_REG_PKT_HDR_WC_MSB 0x63
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#define UB953_REG_CSI_ECC 0x64
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#define UB953_REG_IND_ACC_CTL 0xb0
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#define UB953_REG_IND_ACC_ADDR 0xb1
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#define UB953_REG_IND_ACC_DATA 0xb2
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#define UB953_REG_FPD3_RX_ID(n) (0xf0 + (n))
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#define UB953_REG_FPD3_RX_ID_LEN 6
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/* Indirect register blocks */
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#define UB953_IND_TARGET_PAT_GEN 0x00
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#define UB953_IND_TARGET_FPD3_TX 0x01
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#define UB953_IND_TARGET_DIE_ID 0x02
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#define UB953_IND_PGEN_CTL 0x01
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#define UB953_IND_PGEN_CTL_PGEN_ENABLE BIT(0)
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#define UB953_IND_PGEN_CFG 0x02
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#define UB953_IND_PGEN_CSI_DI 0x03
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#define UB953_IND_PGEN_LINE_SIZE1 0x04
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#define UB953_IND_PGEN_LINE_SIZE0 0x05
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#define UB953_IND_PGEN_BAR_SIZE1 0x06
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#define UB953_IND_PGEN_BAR_SIZE0 0x07
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#define UB953_IND_PGEN_ACT_LPF1 0x08
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#define UB953_IND_PGEN_ACT_LPF0 0x09
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#define UB953_IND_PGEN_TOT_LPF1 0x0a
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#define UB953_IND_PGEN_TOT_LPF0 0x0b
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#define UB953_IND_PGEN_LINE_PD1 0x0c
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#define UB953_IND_PGEN_LINE_PD0 0x0d
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#define UB953_IND_PGEN_VBP 0x0e
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#define UB953_IND_PGEN_VFP 0x0f
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#define UB953_IND_PGEN_COLOR(n) (0x10 + (n)) /* n <= 15 */
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#endif /* __MEDIA_I2C_DS90UB953_H__ */
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