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i.MX dt64 changes for v7.2

Browse Source 
New Board Support:
   Added 15+ new boards including i.MX95 (FRDM PRO, Aquila, Audio Board v2),
   i.MX93/91 (Variscite DART/VAR-SOM), i.MX8 (TQMa8QM, SolidRun i.MX8DXL
   HummingBoard), Toradex Verdin Zinnia variants, and LX2160A Half Twins.
 
 PCIe Improvements:
   Added Root Port nodes and PERST properties across
   iMX8MM/MP/MQ/DXL/QM/QXP/95, new PCIe support for iMX94/943, common M.2
   PCIe overlay, fixed outbound address space configuration
 
 Graphics, Camera and Display:
   Mali G310 GPU for iMX952, HDMI for iMX8MP PhyBoard, extensive DH
   Electronics panel overlays, Extensive overlay ecosystem for DH
   Electronics iMX8MP boards, PhyBoard PEB-AV-18, camera (OV5640), and
   ethernet configuration overlays
 
 Peripheral Support:
   S32G2/G3 PIT/ADC/PWM, iMX8ULP CSI/ISI, iMX943 SD WiFi, USB hub for
   LX2160A, TPM/CAN/ADC support for Variscite boards, Bluetooth and UART
   enhancements for Toradex SMARC boards.
 
 Enhancements
   Added gpio-line-namesacross PhyBOARD platforms. Watchdog reset pinctrl
   configurations for iMX91 boards, Ethernet PHY reset GPIO support.
 
 Bug Fixes:
   Corrected DDR PMU interrupts, SMMU registers, watchdog addresses,
   interrupt flags, GPIO configurations, PHY reset handling, and RS485
   polarity, USDHC signal configurations for PhyCORE SoMs.
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Merge tag 'imx-dt64-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/dt

i.MX dt64 changes for v7.2

New Board Support:
  Added 15+ new boards including i.MX95 (FRDM PRO, Aquila, Audio Board v2),
  i.MX93/91 (Variscite DART/VAR-SOM), i.MX8 (TQMa8QM, SolidRun i.MX8DXL
  HummingBoard), Toradex Verdin Zinnia variants, and LX2160A Half Twins.

PCIe Improvements:
  Added Root Port nodes and PERST properties across
  iMX8MM/MP/MQ/DXL/QM/QXP/95, new PCIe support for iMX94/943, common M.2
  PCIe overlay, fixed outbound address space configuration

Graphics, Camera and Display:
  Mali G310 GPU for iMX952, HDMI for iMX8MP PhyBoard, extensive DH
  Electronics panel overlays, Extensive overlay ecosystem for DH
  Electronics iMX8MP boards, PhyBoard PEB-AV-18, camera (OV5640), and
  ethernet configuration overlays

Peripheral Support:
  S32G2/G3 PIT/ADC/PWM, iMX8ULP CSI/ISI, iMX943 SD WiFi, USB hub for
  LX2160A, TPM/CAN/ADC support for Variscite boards, Bluetooth and UART
  enhancements for Toradex SMARC boards.

Enhancements
  Added gpio-line-namesacross PhyBOARD platforms. Watchdog reset pinctrl
  configurations for iMX91 boards, Ethernet PHY reset GPIO support.

Bug Fixes:
  Corrected DDR PMU interrupts, SMMU registers, watchdog addresses,
  interrupt flags, GPIO configurations, PHY reset handling, and RS485
  polarity, USDHC signal configurations for PhyCORE SoMs.

* tag 'imx-dt64-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: (110 commits)
  arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlays
  arm64: dts: imx93-var-som-symphony: enable ADC
  arm64: dts: imx93-var-som-symphony: enable TPM3 PWM
  arm64: dts: imx93-var-som-symphony: keep RGB_SEL low
  arm64: dts: imx93-var-som-symphony: enable UART7
  arm64: dts: imx93-var-som-symphony: add TPM support
  arm64: dts: imx91-var-som-symphony: fix RGB_SEL handling
  arm64: dts: freescale: fsl-ls1028a-tqmls1028a-mbls1028a: switch mmc aliases
  arm64: dts: imx943-evk-sdwifi: add a new dtso to support SDIW612 WiFi
  arm64: dts: imx8mp-kontron: Fix GPIO for display power switch
  arm64: dts: freescale: imx95-aquila: Add Clover carrier board
  arm64: dts: freescale: add Aquila iMX95 support
  dt-bindings: arm: fsl: add Aquila iMX95
  arm64: dts: tqma8mpql-mba8mpxl: configure sai clock in audio codec as well
  arm64: dts: freescale: add i.MX95 19x19 FRDM PRO board dts
  dt-bindings: arm: fsl: Add i.MX95 19x19 FRDM PRO board
  arm64: dts: s32g: add PWM support for s32g2 and s32g3
  arm64: dts: s32g3: Fix SWT8 watchdog address
  arm64: dts: imx95-var-dart-sonata: add CAN controller
  arm64: dts: imx95-var-dart-sonata: add TPM reset GPIO
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-06-10 22:39:38 +02:00
commit b8d5578e2e
122 changed files with 13347 additions and 267 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -1031,6 +1031,7 @@ properties:
- toradex,verdin-imx8mm-nonwifi-ivy # Verdin iMX8M Mini Module on Ivy
- toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow
- toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia
- toradex,verdin-imx8mm-nonwifi-zinnia # Verdin iMX8M Mini Module on Zinnia
- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
- const: fsl,imx8mm
@ -1043,6 +1044,7 @@ properties:
- toradex,verdin-imx8mm-wifi-ivy # Verdin iMX8M Mini Wi-Fi / BT Module on Ivy
- toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow
- toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia
- toradex,verdin-imx8mm-wifi-zinnia # Verdin iMX8M Mini Wi-Fi / BT Module on Zinnia
- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
- const: fsl,imx8mm
@ -1277,6 +1279,7 @@ properties:
- toradex,verdin-imx8mp-nonwifi-ivy # Verdin iMX8M Plus Module on Ivy
- toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow
- toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia
- toradex,verdin-imx8mp-nonwifi-zinnia # Verdin iMX8M Plus Module on Zinnia
- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
- const: fsl,imx8mp
@ -1289,6 +1292,7 @@ properties:
- toradex,verdin-imx8mp-wifi-ivy # Verdin iMX8M Plus Wi-Fi / BT Module on Ivy
- toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow
- toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia
- toradex,verdin-imx8mp-wifi-zinnia # Verdin iMX8M Plus Wi-Fi / BT Module on Zinnia
- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
- const: fsl,imx8mp
@ -1400,6 +1404,13 @@ properties:
- fsl,imx8dxl-evk # i.MX8DXL EVK Board
- const: fsl,imx8dxl
- description: SolidRun i.MX8DXL SoM based boards
items:
- enum:
- solidrun,imx8dxl-hummingboard-telematics # SolidRun i.MX8DXL SoM EVK Board
- const: solidrun,imx8dxl-sr-som
- const: fsl,imx8dxl
- description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules
items:
- enum:
@ -1464,6 +1475,7 @@ properties:
- description: i.MX91 based Boards
items:
- enum:
- fsl,imx91-9x9-qsb # i.MX91 9x9 QSB Board
- fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board
- fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board
- fsl,imx91-11x11-frdm-s # FRDM i.MX91S Development Board
@ -1488,9 +1500,11 @@ properties:
- description: i.MX95 based Boards
items:
- enum:
- fsl,imx95-15x15-ab2 # i.MX95 15x15 Audio Board V2
- fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board
- fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board
- fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
- fsl,imx95-19x19-frdm-pro # i.MX95 19x19 FRDM PRO Board
- toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK)
- const: fsl,imx95
@ -1507,6 +1521,14 @@ properties:
- const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC
- const: fsl,imx95
- description: Toradex Boards with Aquila iMX95 Modules
items:
- enum:
- toradex,aquila-imx95-clover # Aquila iMX95 Module on Clover Board
- toradex,aquila-imx95-dev # Aquila iMX95 Module on Aquila Development Board
- const: toradex,aquila-imx95 # Aquila iMX95 Module
- const: fsl,imx95
- description: Toradex Boards with SMARC iMX95 Modules
items:
- const: toradex,smarc-imx95-dev # Toradex SMARC iMX95 on Toradex SMARC Development Board
@ -1521,6 +1543,7 @@ properties:
- toradex,verdin-imx95-nonwifi-ivy # Verdin iMX95 Module on Ivy
- toradex,verdin-imx95-nonwifi-mallow # Verdin iMX95 Module on Mallow
- toradex,verdin-imx95-nonwifi-yavia # Verdin iMX95 Module on Yavia
- toradex,verdin-imx95-nonwifi-zinnia # Verdin iMX95 Module on Zinnia
- const: toradex,verdin-imx95-nonwifi # Verdin iMX95 Module without Wi-Fi / BT
- const: toradex,verdin-imx95 # Verdin iMX95 Module
- const: fsl,imx95
@ -1533,6 +1556,7 @@ properties:
- toradex,verdin-imx95-wifi-ivy # Verdin iMX95 Wi-Fi / BT Module on Ivy
- toradex,verdin-imx95-wifi-mallow # Verdin iMX95 Wi-Fi / BT Module on Mallow
- toradex,verdin-imx95-wifi-yavia # Verdin iMX95 Wi-Fi / BT Module on Yavia
- toradex,verdin-imx95-wifi-zinnia # Verdin iMX95 Wi-Fi / BT Module on Zinnia
- const: toradex,verdin-imx95-wifi # Verdin iMX95 Wi-Fi / BT Module
- const: toradex,verdin-imx95 # Verdin iMX95 Module
- const: fsl,imx95
@ -1620,6 +1644,18 @@ properties:
- const: variscite,var-dart-mx91 # Variscite DART-MX91 SOM
- const: fsl,imx91
- description: Variscite VAR-SOM-MX91 based boards
items:
- const: variscite,var-som-mx91-symphony # Variscite VAR-SOM-MX91 on Symphony
- const: variscite,var-som-mx91 # Variscite VAR-SOM-MX91
- const: fsl,imx91
- description: Variscite DART-MX93 based boards
items:
- const: variscite,var-dart-mx93-sonata # Variscite DART-MX93 on Sonata Development Board
- const: variscite,var-dart-mx93 # Variscite DART-MX93 SOM
- const: fsl,imx93
- description: Variscite VAR-SOM-MX93 based boards
items:
- const: variscite,var-som-mx93-symphony
@ -1874,6 +1910,7 @@ properties:
- enum:
- solidrun,clearfog-cx
- solidrun,honeycomb
- solidrun,twins-single
- const: solidrun,lx2160a-cex7
- const: fsl,lx2160a

163
arch/arm64/boot/dts/freescale/Makefile
View File

@ -51,6 +51,8 @@ DTC_FLAGS_fsl-lx2160a-bluebox3-rev-a := -Wno-interrupt_map
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3-rev-a.dtb
DTC_FLAGS_fsl-lx2160a-clearfog-cx := -Wno-interrupt_map
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
DTC_FLAGS_fsl-lx2160a-half-twins := -Wno-interrupt_map
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-half-twins.dtb
DTC_FLAGS_fsl-lx2160a-honeycomb := -Wno-interrupt_map
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
DTC_FLAGS_fsl-lx2160a-qds := -Wno-interrupt_map
@ -111,6 +113,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb
DTC_FLAGS_imx8dxl-hummingboard-telematics := -@
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-hummingboard-telematics.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb
@ -177,11 +181,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-zinnia.dtb
imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo
imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo
@ -206,10 +212,10 @@ imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb
imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo
imx8mn-vhip4-evalboard-v1-overlay-ksz9031-dtbs := imx8mn-vhip4-evalboard-v1.dtb \
imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtbo
imx8mn-vhip4-evalboard-v2-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v2.dtb \
imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo
imx8mn-vhip4-evalboard-v2-overlay-adin1300-dtbs := imx8mn-vhip4-evalboard-v2.dtb \
imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtbo
imx8mn-vhip4-evalboard-v2-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v2.dtb \
imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mn-vhip4-evalboard-v1.dtb \
imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtb \
imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo \
@ -241,9 +247,118 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh-dtbs := \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo
imx8mp-dhcom-pdk2-overlay-531-100-x21-dtbs := \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk2-overlay-531-100-x21.dtbo
imx8mp-dhcom-pdk2-overlay-531-100-x22-dtbs := \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk2-overlay-531-100-x22.dtbo
imx8mp-dhcom-pdk2-overlay-560-300-x12-dtbs := \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk2-overlay-560-300-x12.dtbo
imx8mp-dhcom-pdk2-overlay-eth1xfast-dtbs := \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo
imx8mp-dhcom-pdk2-overlay-eth2xfast-dtbs := \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo
imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtbo
imx8mp-dhcom-pdk3-overlay-531-100-x40-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-531-100-x40.dtbo
imx8mp-dhcom-pdk3-overlay-531-100-x41-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-531-100-x41.dtbo
imx8mp-dhcom-pdk3-overlay-560-300-x36-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-560-300-x36.dtbo
imx8mp-dhcom-pdk3-overlay-732-100-x36-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-732-100-x36.dtbo
imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtbo
imx8mp-dhcom-pdk3-overlay-eth1xfast-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo
imx8mp-dhcom-pdk3-overlay-eth2xfast-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo
imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtbo
imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31-dtbs := \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtb \
imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \
imx8mp-dhcom-pdk2-overlay-531-100-x21.dtb \
imx8mp-dhcom-pdk2-overlay-531-100-x21.dtbo \
imx8mp-dhcom-pdk2-overlay-531-100-x22.dtb \
imx8mp-dhcom-pdk2-overlay-531-100-x22.dtbo \
imx8mp-dhcom-pdk2-overlay-560-300-x12.dtb \
imx8mp-dhcom-pdk2-overlay-560-300-x12.dtbo \
imx8mp-dhcom-pdk2-overlay-eth1xfast.dtb \
imx8mp-dhcom-pdk2-overlay-eth2xfast.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtb \
imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtbo \
imx8mp-dhcom-pdk3-overlay-531-100-x40.dtb \
imx8mp-dhcom-pdk3-overlay-531-100-x40.dtbo \
imx8mp-dhcom-pdk3-overlay-531-100-x41.dtb \
imx8mp-dhcom-pdk3-overlay-531-100-x41.dtbo \
imx8mp-dhcom-pdk3-overlay-560-300-x36.dtb \
imx8mp-dhcom-pdk3-overlay-560-300-x36.dtbo \
imx8mp-dhcom-pdk3-overlay-732-100-x36.dtb \
imx8mp-dhcom-pdk3-overlay-732-100-x36.dtbo \
imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtb \
imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtbo \
imx8mp-dhcom-pdk3-overlay-eth1xfast.dtb \
imx8mp-dhcom-pdk3-overlay-eth2xfast.dtb \
imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtb \
imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtbo \
imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtb \
imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtbo
imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \
imx8mp-dhcom-picoitx.dtb \
imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb \
imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtb \
imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb
@ -345,23 +460,27 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-zinnia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-zinnia.dtb
imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtbo
imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds-hdmi.dtbo
imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo
imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo
imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo
imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx-pcie0-ep.dtbo
imx8mp-evk-pcie-dtbs += imx8mp-evk.dtb imx-m2-pcie.dtbo
imx8mp-evk-pcie-ep-dtbs += imx8mp-evk-pcie.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-lvds-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb
imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo
@ -408,6 +527,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval-v1.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-tqma8qm-mba8x.dtb
imx8qm-mek-ov5640-csi0-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo
dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi0.dtb
@ -438,10 +558,15 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb
imx91-phyboard-segin-peb-av-18-dtbs += imx91-phyboard-segin.dtb imx91-phyboard-segin-peb-av-18.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin-peb-av-18.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo
@ -449,15 +574,18 @@ imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb im
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-rgb-cdtech-dc44.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
imx93-9x9-qsb-can1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1.dtbo
imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo
imx93-9x9-qsb-ontat-kd50g21-40nt-a1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo
imx93-9x9-qsb-tianma-tm050rdh03-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-tianma-tm050rdh03.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-tianma-tm050rdh03.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb
@ -474,6 +602,7 @@ imx93-phyboard-nash-jtag-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-jta
imx93-phyboard-nash-peb-wlbt-07-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-peb-wlbt-07.dtbo
imx93-phyboard-nash-pwm-fan-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-pwm-fan.dtbo
imx93-phyboard-segin-peb-av-02-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-av-02.dtbo
imx93-phyboard-segin-peb-av-18-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-av-18.dtbo
imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-eval-01.dtbo
imx93-phyboard-segin-peb-wlbt-05-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-wlbt-05.dtbo
imx93-phycore-rpmsg-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-segin.dtb imx93-phycore-rpmsg.dtbo
@ -481,6 +610,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-jtag.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-wlbt-07.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-pwm-fan.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-av-02.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-av-18.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-wlbt-05.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb
@ -498,14 +628,26 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb
imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb
imx943-evk-pcie0-ep-dtbs += imx943-evk.dtb imx-pcie0-ep.dtbo
imx943-evk-pcie1-ep-dtbs += imx943-evk.dtb imx-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx943-evk-pcie0-ep.dtb imx943-evk-pcie1-ep.dtb
imx943-evk-sdwifi-dtbs := imx943-evk.dtb imx943-evk-sdwifi.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx943-evk-sdwifi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-ab2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-clover.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb
@ -514,13 +656,18 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-zinnia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-zinnia.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
imx95-15x15-evk-pcie-dtbs += imx95-15x15-evk.dtb imx-m2-pcie.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk-pcie.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo
imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo

4
arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi
View File

@ -17,8 +17,8 @@ aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
mmc0 = &esdhc; /* SD-Card */
mmc1 = &esdhc1; /* eMMC */
mmc0 = &esdhc1; /* eMMC */
mmc1 = &esdhc; /* SD-Card */
serial0 = &duart0;
serial1 = &duart1;
};

41
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
View File

@ -4,10 +4,6 @@
//
// Copyright 2019 SolidRun Ltd.
/dts-v1/;
#include "fsl-lx2160a.dtsi"
/ {
model = "SolidRun LX2160A COM Express Type 7 module";
compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a";
@ -17,6 +13,13 @@ aliases {
rtc0 = &com_rtc;
};
v_1_2: regulator-1-2 {
compatible = "regulator-fixed";
regulator-name = "1v2";
regulator-max-microvolt = <1200000>;
regulator-min-microvolt = <1200000>;
};
sb_3v3: regulator-sb3v3 {
compatible = "regulator-fixed";
regulator-name = "RT7290";
@ -62,7 +65,7 @@ i2c-mux@77 {
#size-cells = <0>;
reg = <0x77>;
i2c@0 {
ddr_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@ -88,7 +91,7 @@ eeprom@57 {
};
};
i2c@1 {
fan_i2c: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
@ -99,7 +102,7 @@ fan-temperature-ctrlr@18 {
};
};
i2c@2 {
power_i2c: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
@ -110,7 +113,7 @@ regulator@5c {
};
};
i2c@3 {
i2c_smb: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
@ -185,10 +188,24 @@ &pinmux_i2crv {
pinctrl-0 = <&gpio0_14_12_pins>;
};
&usb0 {
status = "okay";
};
&usb1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
usb_hub_2_0: hub@1 {
compatible = "usb4b4,6502", "usb4b4,6506";
reg = <1>;
peer-hub = <&usb_hub_3_0>;
vdd2-supply = <&sb_3v3>;
vdd-supply = <&v_1_2>;
};
usb_hub_3_0: hub@2 {
compatible = "usb4b4,6500", "usb4b4,6504";
reg = <2>;
peer-hub = <&usb_hub_2_0>;
vdd2-supply = <&sb_3v3>;
vdd-supply = <&v_1_2>;
};
};

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
View File

@ -6,6 +6,8 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"
/ {

7
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
View File

@ -5,9 +5,6 @@
//
// Copyright 2019 SolidRun Ltd.
/dts-v1/;
#include "fsl-lx2160a-cex7.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
/ {
@ -145,3 +142,7 @@ &uart0 {
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
};

830
arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts Normal file
View File

@ -0,0 +1,830 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for single LX2160A CEX-7 on Twins board.
//
// Copyright 2022 SolidRun Ltd.
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "fsl-lx2160a-rev2.dtsi"
#include "fsl-lx2160a-cex7.dtsi"
/ {
compatible = "solidrun,twins-single", "solidrun,lx2160a-cex7", "fsl,lx2160a";
model = "SolidRun LX2160A SolidWAN Single";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &expander0;
gpio5 = &expander1;
gpio6 = &expander2;
gpio7 = &expander3;
i2c0 = &i2c0;
i2c1 = &i2c2;
i2c2 = &i2c4;
i2c3 = &fan_i2c;
i2c4 = &power_i2c;
i2c5 = &i2c_smb;
i2c6 = &sfp0_i2c;
i2c7 = &sfp1_i2c;
i2c8 = &sfp2_i2c;
i2c9 = &sfp3_i2c;
i2c10 = &twins_sfp_c1_at_i2c;
i2c11 = &twins_sfp_c1_ab_i2c;
i2c12 = &twins_sfp_c1_bt_i2c;
i2c13 = &twins_sfp_c1_bb_i2c;
i2c14 = &twins_sfp_c2_at_i2c;
i2c15 = &twins_sfp_c2_ab_i2c;
i2c16 = &twins_sfp_c2_bt_i2c;
i2c17 = &twins_sfp_c2_bb_i2c;
i2c18 = &twins_sfp_c3_at_i2c;
i2c19 = &twins_sfp_c3_ab_i2c;
i2c20 = &twins_sfp_c3_bt_i2c;
i2c21 = &twins_sfp_c3_bb_i2c;
i2c22 = &htwins_sfp_c3_at_i2c;
i2c23 = &htwins_sfp_c3_ab_i2c;
i2c24 = &htwins_sfp_c3_bt_i2c;
i2c25 = &htwins_sfp_c3_bb_i2c;
i2c26 = &ddr_i2c;
mmc0 = &esdhc0;
mmc1 = &esdhc1;
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led_ht_c3_bt: led-sfp-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
gpios = <&expander3 14 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac5>;
linux,default-trigger = "netdev";
};
led_ht_c3_bb: led-sfp-2 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
gpios = <&expander3 13 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac15>;
linux,default-trigger = "netdev";
};
led_ht_c3_at: led-sfp-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <3>;
gpios = <&expander3 11 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac6>;
linux,default-trigger = "netdev";
};
led_ht_c3_ab: led-sfp-4 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <4>;
gpios = <&expander3 12 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac11>;
linux,default-trigger = "netdev";
};
led_c1_bt: led-sfp-9 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <9>;
gpios = <&expander1 4 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac4>;
linux,default-trigger = "netdev";
};
led_c1_bb: led-sfp-10 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <10>;
gpios = <&expander1 3 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac17>;
linux,default-trigger = "netdev";
};
led_c1_at: led-sfp-11 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <11>;
gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac3>;
linux,default-trigger = "netdev";
};
led_c1_ab: led-sfp-12 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <12>;
gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac12>;
linux,default-trigger = "netdev";
};
led_c2_bt: led-sfp-13 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <13>;
gpios = <&expander1 10 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac8>;
linux,default-trigger = "netdev";
};
led_c2_bb: led-sfp-14 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <14>;
gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac16>;
linux,default-trigger = "netdev";
};
led_c2_at: led-sfp-15 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <15>;
gpios = <&expander1 5 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac7>;
linux,default-trigger = "netdev";
};
led_c2_ab: led-sfp-16 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <16>;
gpios = <&expander1 6 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac18>;
linux,default-trigger = "netdev";
};
led_c3_bt: led-sfp-17 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <17>;
gpios = <&expander1 14 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac10>;
linux,default-trigger = "netdev";
};
led_c3_bb: led-sfp-18 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <18>;
gpios = <&expander1 13 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac14>;
linux,default-trigger = "netdev";
};
led_c3_at: led-sfp-19 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <19>;
gpios = <&expander1 11 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac9>;
linux,default-trigger = "netdev";
};
led_c3_ab: led-sfp-20 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_LAN;
function-enumerator = <20>;
gpios = <&expander1 12 GPIO_ACTIVE_LOW>;
trigger-sources = <&dpmac13>;
linux,default-trigger = "netdev";
};
led-status {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <0>;
gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led-status-twin {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
};
led-fault {
color = <LED_COLOR_ID_YELLOW>;
default-state = "off";
function = LED_FUNCTION_FAULT;
function-enumerator = <0>;
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
panic-indicator;
};
led-fault-twin {
color = <LED_COLOR_ID_YELLOW>;
default-state = "off";
function = LED_FUNCTION_FAULT;
function-enumerator = <1>;
gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
};
};
mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
/*
* This gpio controlled mux can route the tacho signals of 6 PWM FAN connectors
* to the tacho inputs of both CEX-7 modules (twins).
*
* The first twin controls this mux and monitors four fan connectors, two intended
* for itself, and two for the OCP card.
*
* The second twin monitors only two fan connectors intended for itself.
*
* The table below maps selector GPIO states to monitored fan connector per twin:
*
* | SEL1 | SEL0 | Twin 1 | Twin 2 |
* | ---: | ---: | :------| ------ |
* | 0 | 0 | J10 | J5024 |
* | 0 | 1 | J5016 | J5024 |
* | 1 | 0 | J5026 | J5025 |
* | 1 | 1 | J5013 | J5025 |
*/
mux-gpios = <&expander0 8 GPIO_ACTIVE_HIGH>, /* SEL0 */
<&expander0 15 GPIO_ACTIVE_HIGH>; /* SEL1 */
};
ht_c3_bt_sfp: sfp-1 {
compatible = "sff,sfp";
i2c-bus = <&htwins_sfp_c3_bt_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander2 13 GPIO_ACTIVE_LOW>;
};
ht_c3_bb_sfp: sfp-2 {
compatible = "sff,sfp";
i2c-bus = <&htwins_sfp_c3_bb_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander2 14 GPIO_ACTIVE_LOW>;
};
ht_c3_at_sfp: sfp-3 {
compatible = "sff,sfp";
i2c-bus = <&htwins_sfp_c3_at_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander2 11 GPIO_ACTIVE_LOW>;
};
ht_c3_ab_sfp: sfp-4 {
compatible = "sff,sfp";
i2c-bus = <&htwins_sfp_c3_ab_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander2 12 GPIO_ACTIVE_LOW>;
};
c1_bt_sfp: sfp-9 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c1_bt_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
};
c1_bb_sfp: sfp-10 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c1_bb_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 4 GPIO_ACTIVE_LOW>;
};
c1_at_sfp: sfp-11 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c1_at_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
};
c1_ab_sfp: sfp-12 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c1_ab_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
};
c2_bt_sfp: sfp-13 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c2_bt_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 9 GPIO_ACTIVE_LOW>;
};
c2_bb_sfp: sfp-14 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c2_bb_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 10 GPIO_ACTIVE_LOW>;
};
c2_at_sfp: sfp-15 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c2_at_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
};
c2_ab_sfp: sfp-16 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c2_ab_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
};
c3_bt_sfp: sfp-17 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c3_bt_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 13 GPIO_ACTIVE_LOW>;
};
c3_bb_sfp: sfp-18 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c3_bb_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 14 GPIO_ACTIVE_LOW>;
};
c3_at_sfp: sfp-19 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c3_at_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 11 GPIO_ACTIVE_LOW>;
};
c3_ab_sfp: sfp-20 {
compatible = "sff,sfp";
i2c-bus = <&twins_sfp_c3_ab_i2c>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};
};
/*
* This board supports industrial grade temperatures,
* the LX2160A SoC maximum junction temperature is 105°C.
*
* Raise thermal thresholds to allow operation near maximum temperature.
*/
&ccn_dpaa_alert {
temperature = <100000>;
};
&ccn_dpaa_crit {
temperature = <105000>;
};
&cluster2_3_alert {
temperature = <100000>;
};
&cluster2_3_crit {
temperature = <105000>;
};
&cluster4_alert {
temperature = <100000>;
};
&cluster4_crit {
temperature = <105000>;
};
&cluster5_alert {
temperature = <100000>;
};
&cluster5_crit {
temperature = <105000>;
};
&cluster6_7_alert {
temperature = <100000>;
};
&cluster6_7_crit {
temperature = <105000>;
};
&dce_qbman_alert {
temperature = <100000>;
};
&dce_qbman_crit {
temperature = <105000>;
};
/* sfp port 11 */
&dpmac3 {
managed = "in-band-status";
phys = <&serdes_1 7>;
sfp = <&c1_at_sfp>;
};
/* sfp port 9 */
&dpmac4 {
managed = "in-band-status";
phys = <&serdes_1 6>;
sfp = <&c1_bt_sfp>;
};
/* sfp port 1 */
&dpmac5 {
managed = "in-band-status";
phys = <&serdes_1 5>;
sfp = <&ht_c3_bt_sfp>;
};
/* sfp port 3 */
&dpmac6 {
managed = "in-band-status";
phys = <&serdes_1 4>;
sfp = <&ht_c3_at_sfp>;
};
/* sfp port 15 */
&dpmac7 {
managed = "in-band-status";
phys = <&serdes_1 3>;
sfp = <&c2_at_sfp>;
};
/* sfp port 13 */
&dpmac8 {
managed = "in-band-status";
phys = <&serdes_1 2>;
sfp = <&c2_bt_sfp>;
};
/* sfp port 19 */
&dpmac9 {
managed = "in-band-status";
phys = <&serdes_1 1>;
sfp = <&c3_at_sfp>;
};
/* sfp port 17 */
&dpmac10 {
managed = "in-band-status";
phys = <&serdes_1 0>;
sfp = <&c3_bt_sfp>;
};
/* sfp port 4 */
&dpmac11 {
managed = "in-band-status";
phys = <&serdes_2 0>;
sfp = <&ht_c3_ab_sfp>;
};
/* sfp port 12 */
&dpmac12 {
managed = "in-band-status";
phys = <&serdes_2 1>;
sfp = <&c1_ab_sfp>;
};
/* sfp port 20 */
&dpmac13 {
managed = "in-band-status";
phys = <&serdes_2 6>;
sfp = <&c3_ab_sfp>;
};
/* sfp port 18 */
&dpmac14 {
managed = "in-band-status";
phys = <&serdes_2 7>;
sfp = <&c3_bb_sfp>;
};
/* sfp port 2 */
&dpmac15 {
managed = "in-band-status";
phys = <&serdes_2 4>;
sfp = <&ht_c3_bb_sfp>;
};
/* sfp port 14 */
&dpmac16 {
managed = "in-band-status";
phys = <&serdes_2 5>;
sfp = <&c2_bb_sfp>;
};
/* sfp port 10 */
&dpmac17 {
/* override connection to on-COM phy */
/delete-property/ phy-handle;
/delete-property/ phy-connection-type;
managed = "in-band-status";
phys = <&serdes_2 2>;
sfp = <&c1_bb_sfp>;
};
/* sfp port 16 */
&dpmac18 {
managed = "in-band-status";
phys = <&serdes_2 3>;
sfp = <&c2_ab_sfp>;
};
&esdhc0 {
pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
pinctrl-names = "default";
/*
* Disable 1.8V modes so that microsd state is same between
* power-on-reset, u-boot and linux.
* This avoids sporadic read errors after hard reset with some cards.
*/
no-1-8-v;
status = "okay";
};
&i2c2 {
expander0: gpio@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
#gpio-cells = <2>;
gpio-controller;
};
expander1: gpio@21 {
compatible = "nxp,pca9555";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
};
expander2: gpio@24 {
compatible = "nxp,pca9555";
reg = <0x24>;
#gpio-cells = <2>;
gpio-controller;
};
expander3: gpio@25 {
compatible = "nxp,pca9555";
reg = <0x25>;
#gpio-cells = <2>;
gpio-controller;
};
/* Half twins configuration; take over c3 from the other twin side */
i2c-mux@73 {
compatible = "nxp,pca9547";
reg = <0x73>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
htwins_sfp_c3_at_i2c: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
htwins_sfp_c3_ab_i2c: i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
};
htwins_sfp_c3_bt_i2c: i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
htwins_sfp_c3_bb_i2c: i2c@6 {
reg = <6>;
#address-cells = <1>;
#size-cells = <0>;
};
};
i2c-mux@76 {
compatible = "nxp,pca9547";
reg = <0x76>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
twins_sfp_c1_at_i2c: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c1_ab_i2c: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c1_bt_i2c: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c1_bb_i2c: i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c2_at_i2c: i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c2_ab_i2c: i2c@6 {
reg = <6>;
#address-cells = <1>;
#size-cells = <0>;
};
};
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
twins_sfp_c2_bt_i2c: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c2_bb_i2c: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c3_at_i2c: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c3_ab_i2c: i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c3_bt_i2c: i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
twins_sfp_c3_bb_i2c: i2c@6 {
reg = <6>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&pcie5 {
status = "okay";
};
&pcs_mdio3 {
status = "okay";
};
&pcs_mdio4 {
status = "okay";
};
&pcs_mdio5 {
status = "okay";
};
&pcs_mdio6 {
status = "okay";
};
&pcs_mdio7 {
status = "okay";
};
&pcs_mdio8 {
status = "okay";
};
&pcs_mdio9 {
status = "okay";
};
&pcs_mdio10 {
status = "okay";
};
&pcs_mdio11 {
status = "okay";
};
&pcs_mdio12 {
status = "okay";
};
&pcs_mdio13 {
status = "okay";
};
&pcs_mdio14 {
status = "okay";
};
&pcs_mdio15 {
status = "okay";
};
&pcs_mdio16 {
status = "okay";
};
&pcs_mdio17 {
status = "okay";
};
&pcs_mdio18 {
status = "okay";
};
&rgmii_phy1 {
/*
* COM has a phy at address 1 connected to SoC Ethernet Controller 1.
* It competes for WRIOP MAC17, and no connector has been wired.
*/
status = "disabled";
};
&serdes_2 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&wriop_alert {
temperature = <100000>;
};
&wriop_crit {
temperature = <105000>;
};

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts
View File

@ -6,6 +6,8 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"
/ {

48
arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
View File

@ -14,8 +14,12 @@ &pcie1 {
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0xc0000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@ -30,8 +34,12 @@ &pcie2 {
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0xc0000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@ -46,8 +54,12 @@ &pcie3 {
0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0xc0000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@ -63,8 +75,12 @@ &pcie4 {
0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0xc0000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@ -79,8 +95,12 @@ &pcie5 {
0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0xc0000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@ -95,8 +115,12 @@ &pcie6 {
0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0xc0000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";

24
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -499,13 +499,13 @@ ddr-ctrl5-thermal {
thermal-sensors = <&tmu 1>;
trips {
ddr-cluster5-alert {
cluster5_alert: ddr-cluster5-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
ddr-cluster5-crit {
cluster5_crit: ddr-cluster5-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@ -519,13 +519,13 @@ wriop-thermal {
thermal-sensors = <&tmu 2>;
trips {
wriop-alert {
wriop_alert: wriop-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
wriop-crit {
wriop_crit: wriop-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@ -539,13 +539,13 @@ dce-thermal {
thermal-sensors = <&tmu 3>;
trips {
dce-qbman-alert {
dce_qbman_alert: dce-qbman-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
dce-qbman-crit {
dce_qbman_crit: dce-qbman-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@ -559,13 +559,13 @@ ccn-thermal {
thermal-sensors = <&tmu 4>;
trips {
ccn-dpaa-alert {
ccn_dpaa_alert: ccn-dpaa-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
ccn-dpaa-crit {
ccn_dpaa_crit: ccn-dpaa-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@ -579,13 +579,13 @@ cluster4-thermal {
thermal-sensors = <&tmu 5>;
trips {
clust4-hsio3-alert {
cluster4_alert: clust4-hsio3-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
clust4-hsio3-crit {
cluster4_crit: clust4-hsio3-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@ -599,13 +599,13 @@ cluster2-3-thermal {
thermal-sensors = <&tmu 6>;
trips {
cluster2-3-alert {
cluster2_3_alert: cluster2-3-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cluster2-3-crit {
cluster2_3_crit: cluster2-3-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";

37
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
View File

@ -6,7 +6,9 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include <dt-bindings/leds/common.h>
#include "fsl-lx2160a-rev2.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"
/ {
@ -14,7 +16,6 @@ / {
compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
aliases {
crypto = &crypto;
i2c0 = &i2c0;
i2c1 = &i2c2;
i2c2 = &i2c4;
@ -39,6 +40,9 @@ leds {
compatible = "gpio-leds";
led_sfp_at: led-sfp-at {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
default-state = "off";
linux,default-trigger = "netdev";
@ -46,6 +50,9 @@ led_sfp_at: led-sfp-at {
};
led_sfp_ab: led-sfp-ab {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
default-state = "off";
linux,default-trigger = "netdev";
@ -53,6 +60,9 @@ led_sfp_ab: led-sfp-ab {
};
led_sfp_bt: led-sfp-bt {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <3>;
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
default-state = "off";
linux,default-trigger = "netdev";
@ -60,6 +70,9 @@ led_sfp_bt: led-sfp-bt {
};
led_sfp_bb: led-sfp-bb {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <4>;
gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
default-state = "off";
linux,default-trigger = "netdev";
@ -124,42 +137,36 @@ &dpmac11 {
phys = <&serdes_2 0>;
phy-handle = <&ethernet_phy3>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac12 {
phys = <&serdes_2 1>;
phy-handle = <&ethernet_phy1>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac13 {
phys = <&serdes_2 6>;
phy-handle = <&ethernet_phy6>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac14 {
phys = <&serdes_2 7>;
phy-handle = <&ethernet_phy8>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac15 {
phys = <&serdes_2 4>;
phy-handle = <&ethernet_phy4>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac16 {
phys = <&serdes_2 5>;
phy-handle = <&ethernet_phy2>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac17 {
@ -170,14 +177,12 @@ &dpmac17 {
phys = <&serdes_2 2>;
phy-handle = <&ethernet_phy5>;
phy-connection-type = "sgmii";
status = "okay";
};
&dpmac18 {
phys = <&serdes_2 3>;
phy-handle = <&ethernet_phy7>;
phy-connection-type = "sgmii";
status = "okay";
};
&emdio1 {
@ -314,14 +319,6 @@ pcieclk_i2c: i2c@2 {
};
};
&pcie3 {
status = "disabled";
};
&pcie4 {
status = "disabled";
};
&pcs_mdio3 {
status = "okay";
};
@ -370,10 +367,6 @@ &pcs_mdio18 {
status = "okay";
};
&serdes_1 {
status = "okay";
};
&serdes_2 {
status = "okay";
};

15
arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
/dts-v1/;
/plugin/;
&pcie0 {
status = "okay";
};
&m2_usdhc {
status = "disabled";
};

11
arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
View File

@ -78,6 +78,17 @@ pcieb: pcie@5f010000 {
power-domains = <&pd IMX_SC_R_PCIE_B>;
fsl,max-link-speed = <3>;
status = "disabled";
pcieb_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcieb_ep: pcie-ep@5f010000 {

7
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@ -675,6 +675,7 @@ &pcie0 {
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcieb>;
vpcie3v3aux-supply = <&reg_pcieb>;
@ -686,11 +687,13 @@ &pcie0_ep {
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcieb>;
status = "disabled";
};
&pcieb_port0 {
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
};
&sai0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai0>;

560
arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts Normal file
View File

@ -0,0 +1,560 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022-2026 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include "imx8dxl-sr-som.dtsi"
/ {
compatible = "solidrun,imx8dxl-hummingboard-telematics",
"solidrun,imx8dxl-sr-som", "fsl,imx8dxl";
model = "SolidRun i.MX8DXL HummingBoard Telematics";
aliases {
/* override ethernet aliases from imx8dxl.dtsi */
ethernet0 = &eqos;
ethernet1 = &switch_port1;
ethernet2 = &switch_port2;
ethernet3 = &switch_port3;
ethernet4 = &switch_port4;
ethernet5 = &switch_port5;
ethernet6 = &switch_port6;
ethernet7 = &switch_port7;
ethernet8 = &switch_port8;
ethernet9 = &switch_port9;
ethernet10 = &switch_port10;
gpio8 = &tca6408_u2;
mmc2 = &usdhc3;
rtc0 = &carrier_rtc;
rtc1 = &rtc;
serial1 = &lpuart1;
};
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
v_1_1: regulator-1-1 {
compatible = "regulator-fixed";
regulator-name = "1v1";
pinctrl-0 = <&regulator_1v1_pins>;
pinctrl-names = "default";
regulator-always-on;
regulator-max-microvolt = <1100000>;
regulator-min-microvolt = <1100000>;
vin-supply = <&v_5_0>;
gpio = <&lsio_gpio4 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
v_5_0: regulator-5-0 {
compatible = "regulator-fixed";
regulator-name = "5v0";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
/* can transceiver builtin regulator (STBN1 pin) */
reg_flexcan1_stby: regulator-flexcan1-standby {
compatible = "regulator-fixed";
regulator-name = "flexcan1-standby";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&tca6408_u2 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/* can transceiver builtin regulator (STBN2 pin) */
reg_flexcan2_stby: regulator-flexcan2-standby {
compatible = "regulator-fixed";
regulator-name = "flexcan2-standby";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&tca6408_u2 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
modem_vbat: regulator-modem-vbat {
compatible = "regulator-fixed";
regulator-name = "modem-vbat";
pinctrl-0 = <&regulator_modem_vbat_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <3600000>;
regulator-min-microvolt = <3600000>;
vin-supply = <&v_5_0>;
gpio = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
/*
* Cellular Modem uses VBAT, RESET_N and PWRKEY for
* power-sequencing. USB core does not currently
* support this, keep vbat on permanently and let
* userspace deal with reset/pwrkey.
*/
regulator-always-on;
regulator-boot-on;
};
vbus1: regulator-vbus-1 {
compatible = "regulator-fixed";
regulator-name = "vbus1";
pinctrl-0 = <&regulator_usb1_vbus_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
gpio = <&lsio_gpio0 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_LOW>;
};
};
&dma_apbh {
status = "disabled";
};
&eqos {
/* delays are added by connected ethernet-switch cpu port */
phy-mode = "rgmii-id";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
pinctrl-0 = <&eqos_pins>;
pinctrl-names = "default";
status = "okay";
fixed-link {
full-duplex;
speed = <1000>;
};
};
&flexcan1 {
pinctrl-0 = <&flexcan1_pins>;
pinctrl-names = "default";
xceiver-supply = <&reg_flexcan1_stby>;
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&flexcan2 {
pinctrl-0 = <&flexcan2_pins>;
pinctrl-names = "default";
xceiver-supply = <&reg_flexcan2_stby>;
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&i2c2 {
/* routed to J14: SDA(51), SCL(53) */
/* regulator@18 */
tca6408_u2: gpio@20 {
compatible = "ti,tca6408";
reg = <0x20>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "DIG_IN1", "DIG_IN2", "CAN_STNB1", "CAN_STNB2",
"DIG_OUT1", "DIG_OUT2", "", "";
interrupts-extended = <&lsio_gpio0 20 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&tca6408_u2_int_pins>;
pinctrl-names = "default";
};
carrier_rtc: rtc@32 {
compatible = "epson,rx8111";
reg = <0x32>;
};
};
&iomuxc {
bluetooth_pins: pinctrl-bluetooth-grp {
fsl,pins = <
/* BT_REG_ON: io without pull (module integrates pd) */
IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 0x0000061
>;
};
eqos_pins: pinctrl-eqos-grp {
fsl,pins = <
/* MDIO to Switch */
/* enet0 mdio pads supplied with 3.3v */
/* IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT */
IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
/* RGMII to Switch */
IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
>;
};
flexcan1_pins: pinctrl-flexcan1-grp {
fsl,pins = <
IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x00000021
IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x00000021
>;
};
flexcan2_pins: pinctrl-flexcan2-grp {
fsl,pins = <
IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x00000021
IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x00000021
>;
};
lpspi0_pins: pinctrl-lpspi0-grp {
fsl,pins = <
IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK 0x600004c
IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO 0x600004c
IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI 0x600004c
IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 0x0000021
IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 0x0000021
>;
};
lpuart1_pins: pinctrl-lpuart1-grp {
fsl,pins = <
IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
>;
};
modem_pins: pinctrl-lte-grp {
fsl,pins = <
/* modem RESET_N: io open drain drive 2mA */
IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 0x2000061
/* modem PWRKEY: io open drain with pull-up, drive 2mA */
IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 0x2000021
>;
};
regulator_1v1_pins: pinctrl-regulator-1-1-grp {
fsl,pins = <
/* SW_PE: io without pull-up */
IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0000061
>;
};
regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp {
fsl,pins = <
/*
* RF_PWR: io without pull-up,
* has either external pull-up (R1117) or pull-down (R1118).
* With pull-up Modem will boot at system power-up,
* with pull-down modem will enter power-down mode once
* vbat is enabled -> toggle pwrkey to boot modem.
* Hence pull-up (R1117) is preferred.
*/
IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 0x0000061
>;
};
regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp {
fsl,pins = <
/* regulator enable: open-drain with pull-up & low drive strength */
IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 0x2000021
>;
};
switch_pins: pinctrl-switch-grp {
fsl,pins = <
/* SW_RSTn: io without pull-up */
IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0000021
/* SW_CORE_RSTn: io without pull-up */
IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0000021
/* INT_N: io without pull-up */
IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0000021
>;
};
tca6408_u2_int_pins: pinctrl-tca6408-u2-int-grp {
fsl,pins = <
/* gpio-expander interrupt: io with pull-up */
IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 0x0000021
>;
};
usdhc3_pins: pinctrl-usdhc3-grp {
fsl,pins = <
IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK 0x06000040
IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD 0x00000021
IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 0x00000021
IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 0x00000021
IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 0x00000021
IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 0x00000021
>;
};
wifi_pins: pinctrl-wifi-grp {
fsl,pins = <
/* WL_REG_ON: io without pull (module integrates pd) */
IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 0x0000061
>;
};
};
&lpspi0 {
cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>, <&lsio_gpio1 7 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&lpspi0_pins>, <&switch_pins>;
pinctrl-names = "default";
status = "okay";
ethernet-switch@0 {
compatible = "nxp,sja1110a";
reg = <0>;
reset-gpios = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>;
spi-max-frequency = <4000000>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
/* 100Base-TX on connector J26 */
switch_port1: port@1 {
reg = <0x1>;
phy-handle = <&switch_port1_base_tx_phy>;
phy-mode = "internal";
};
/* CPU */
switch_port2: port@2 {
reg = <0x2>;
ethernet = <&eqos>;
phy-mode = "rgmii-id";
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
fixed-link {
full-duplex;
speed = <1000>;
};
};
/* sgmii on addon board connector J21 */
switch_port3: port@3 {
reg = <0x3>;
status = "disabled";
};
/* sgmii on addon board connector J21 */
switch_port4: port@4 {
reg = <0x4>;
status = "disabled";
};
/* 100base-t1 on addon board connector J21 */
switch_port5: port@5 {
reg = <0x5>;
phy-handle = <&switch_port5_base_t1_phy>;
phy-mode = "internal";
status = "disabled";
};
/* 100base-t1 on addon board connector J21 */
switch_port6: port@6 {
reg = <0x6>;
phy-handle = <&switch_port6_base_t1_phy>;
phy-mode = "internal";
status = "disabled";
};
/* 100base-t1 on addon board connector J21 */
switch_port7: port@7 {
reg = <0x7>;
phy-handle = <&switch_port7_base_t1_phy>;
phy-mode = "internal";
status = "disabled";
};
/* 100base-t1 on addon board connector J21 */
switch_port8: port@8 {
reg = <0x8>;
phy-handle = <&switch_port8_base_t1_phy>;
phy-mode = "internal";
status = "disabled";
};
/* 100base-t1 on addon board connector J21 */
switch_port9: port@9 {
reg = <0x9>;
phy-handle = <&switch_port9_base_t1_phy>;
phy-mode = "internal";
status = "disabled";
};
/* 100Base-T1 on connector J26 */
switch_port10: port@a {
reg = <0xa>;
phy-handle = <&switch_port10_base_t1_phy>;
phy-mode = "internal";
};
};
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
compatible = "nxp,sja1110-base-t1-mdio";
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
/* 100base-t1 on addon board connector J21 */
switch_port5_base_t1_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
status = "disabled";
};
/* 100base-t1 on addon board connector J21 */
switch_port6_base_t1_phy: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
status = "disabled";
};
/* 100base-t1 on addon board connector J21 */
switch_port7_base_t1_phy: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
status = "disabled";
};
/* 100base-t1 on addon board connector J21 */
switch_port8_base_t1_phy: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
status = "disabled";
};
/* 100base-t1 on addon board connector J21 */
switch_port9_base_t1_phy: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x5>;
status = "disabled";
};
/* 100Base-T1 on connector J26 */
switch_port10_base_t1_phy: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x6>;
};
};
mdio@1 {
compatible = "nxp,sja1110-base-tx-mdio";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* 100Base-TX on connector J26 */
switch_port1_base_tx_phy: ethernet-phy@1 {
reg = <0x1>;
};
};
};
};
};
/* bluetooth */
&lpuart1 {
pinctrl-0 = <&lpuart1_pins>, <&bluetooth_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4345c5";
clocks = <&osc_32k>;
clock-names = "lpo";
/* Murata 1MW module supports max. 3M baud */
max-speed = <3000000>;
shutdown-gpios = <&lsio_gpio0 13 GPIO_ACTIVE_HIGH>;
/* link fixed supplies to avoid fall-back lookup by name */
vbat-supply = <&v_3_3>;
vddio-supply = <&v_1_8>;
};
};
&lsio_gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "CELL_RESET_N", "CELL_PWRKEY", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&usbotg1 {
dr_mode = "host";
vbus-supply = <&vbus1>;
};
/* cellular modem */
&usbotg2 {
#address-cells = <1>;
#size-cells = <0>;
adp-disable;
disable-over-current;
dr_mode = "host";
hnp-disable;
pinctrl-0 = <&modem_pins>;
pinctrl-names = "default";
power-active-high;
srp-disable;
vbus-supply = <&v_5_0>;
status = "okay";
usb-device@1 {
compatible = "usb2c7c,125";
reg = <1>;
vbus-supply = <&v_3_3>;
vdd-supply = <&modem_vbat>;
};
};
&usbphy2 {
status = "okay";
};
/* WiFi */
&usdhc3 {
bus-width = <4>;
cap-sdio-irq;
mmc-pwrseq = <&usdhc3_pwrseq>;
non-removable;
no-sd;
pinctrl-0 = <&usdhc3_pins>, <&wifi_pins>;
pinctrl-names = "default";
vmmc-supply = <&v_3_3>;
vqmmc-supply = <&v_1_8>;
status = "okay";
};

458
arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi Normal file
View File

@ -0,0 +1,458 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022-2026 Josua Mayer <josua@solid-run.com>
*/
#include "imx8dxl.dtsi"
/ {
compatible = "solidrun,imx8dxl-sr-som", "fsl,imx8dxl";
model = "SolidRun i.MX8DXL SoM";
aliases {
i2c2 = &i2c2;
i2c3 = &i2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart0;
serial2 = &lpuart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
imx8dxl-cm4 {
compatible = "fsl,imx8qxp-cm4";
clocks = <&clk_dummy>;
mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
mbox-names = "tx", "rx", "rxdb";
memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
fsl,entry-address = <0x34fe0000>;
fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
};
pps {
compatible = "pps-gpio";
gpios = <&lsio_gpio2 6 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&gnss_pps_pins>;
pinctrl-names = "default";
};
v_1_2: regulator-1-2 {
compatible = "regulator-fixed";
regulator-name = "1v2";
pinctrl-0 = <&regulator_1_2_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <1200000>;
regulator-min-microvolt = <1200000>;
gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
v_1_6: regulator-1-6 {
compatible = "regulator-fixed";
regulator-name = "1v6";
pinctrl-0 = <&regulator_1_6_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <1600000>;
regulator-min-microvolt = <1600000>;
vin-supply = <&v_1_8>;
gpio = <&lsio_gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
v_1_8: regulator-1-8 {
compatible = "regulator-fixed";
regulator-name = "1v8";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
v_1_8_se: regulator-1-8-secure-element {
compatible = "regulator-fixed";
regulator-name = "1v8-se";
pinctrl-0 = <&regulator_1_8_se_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
vin-supply = <&v_1_8>;
gpio = <&lsio_gpio3 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
v_3_3: regulator-3-3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x98000000 0 0x14000000>;
reusable;
size = <0 0x14000000>;
linux,cma-default;
};
vdev0vring0: memory0@90000000 {
reg = <0 0x90000000 0 0x8000>;
no-map;
};
vdev0vring1: memory@90008000 {
reg = <0 0x90008000 0 0x8000>;
no-map;
};
vdev1vring0: memory@90010000 {
reg = <0 0x90010000 0 0x8000>;
no-map;
};
vdev1vring1: memory@90018000 {
reg = <0 0x90018000 0 0x8000>;
no-map;
};
rsc_table: memory-rsc-table@900ff000 {
reg = <0 0x900ff000 0 0x1000>;
no-map;
};
vdevbuffer: memory-vdevbuffer@90400000 {
compatible = "shared-dma-pool";
reg = <0 0x90400000 0 0x100000>;
no-map;
};
/*
* Memory reserved for optee usage. Please do not use.
* This will be automatically added to dtb if OP-TEE is installed.
* optee@96000000 {
* reg = <0 0x96000000 0 0x2000000>;
* no-map;
* };
*/
};
memory@80000000 {
reg = <0x00000000 0x80000000 0 0x40000000>;
device_type = "memory";
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_gpio_pins>;
pinctrl-names = "default", "gpio";
scl-gpios = <&lsio_gpio3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&lsio_gpio3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-0 = <&i2c3_pins>;
pinctrl-1 = <&i2c3_gpio_pins>;
pinctrl-names = "default", "gpio";
scl-gpios = <&lsio_gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&lsio_gpio3 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
magnetometer@1e {
compatible = "st,iis2mdc";
reg = <0x1e>;
interrupt-parent = <&lsio_gpio2>;
interrupts = <10 IRQ_TYPE_EDGE_RISING>;
pinctrl-0 = <&magnetometer_pins>;
pinctrl-names = "default";
st,drdy-int-pin = <1>;
};
/* pressure-sensor@5c */
inertial-sensor@6b {
compatible = "st,ism330dhcx";
reg = <0x6b>;
interrupt-parent = <&lsio_gpio2>;
interrupts = <11 IRQ_TYPE_EDGE_RISING>;
pinctrl-0 = <&imu_pins>;
pinctrl-names = "default";
st,drdy-int-pin = <1>;
};
};
&iomuxc {
pinctrl-0 = <&pinctrl_hog>;
pinctrl-names = "default";
pinctrl_hog: hoggrp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
>;
};
dsrc_pins: pinctrl-dsrc-grp {
fsl,pins = <
/* reset: io without pull */
IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 0x0000060
/*
* boot0: io without pull
* After reset, this pin selects radio boot media:
* - 0: flash spi
* - 1: slave sdio
* Once the firmware boots however, the radio controls
* this pin for flow-control to signal readiness.
*/
IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 0x0000060
>;
};
gnss_pins: pinctrl-gnss-grp {
fsl,pins = <
/* gps reset: input with pull-up */
IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN 0x0000021
/* gps interrupt: io without pull-up */
IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN 0x0000061
>;
};
gnss_pps_pins: pinctrl-gnss-pps-grp {
fsl,pins = <
/* gps timepulse: input without pull-up */
IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN 0x0000061
>;
};
i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {
fsl,pins = <
/* io with pull-up and weak drive */
IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 0x00000021
/* io with pull-up, weak drive, open-drain */
IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 0x02000021
>;
};
i2c2_pins: pinctrl-i2c2-grp {
fsl,pins = <
/* io with pull-up and weak drive */
IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
>;
};
i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {
fsl,pins = <
/* io with pull-up and weak drive */
IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 0x00000021
/* io with pull-up, weak drive, open-drain */
IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 0x02000021
>;
};
i2c3_pins: pinctrl-i2c3-grp {
fsl,pins = <
/* io with pull-up and weak drive */
IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
>;
};
imu_pins: pinctrl-imu-grp {
fsl,pins = <
/* interrupt: io with pull-down */
IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN 0x0000041
>;
};
lpspi2_pins: pinctrl-lpspi2-grp {
fsl,pins = <
IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 0x600004c
IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 0x600004c
IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 0x600004c
IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 0x6000021
>;
};
lpuart0_pins: pinctrl-lpuart0-grp {
fsl,pins = <
IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
lpuart2_pins: pinctrl-lpuart2-grp {
fsl,pins = <
IMX8DXL_UART2_TX_ADMA_UART2_TX 0x06000020
IMX8DXL_UART2_RX_ADMA_UART2_RX 0x06000020
>;
};
magnetometer_pins: pinctrl-magnetometer-grp {
fsl,pins = <
/* interrupt: io with pull-down */
IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN 0x0000041
>;
};
regulator_1_2_pins: pinctrl-regulator-1-2-grp {
fsl,pins = <
/* io without pull-up */
/* has etxernal pull-down */
IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 0x0000061
>;
};
regulator_1_6_pins: pinctrl-regulator-1-6-grp {
fsl,pins = <
/* io without pull-up */
/* has etxernal pull-down */
IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 0x0000061
>;
};
regulator_1_8_se_pins: pinctrl-regulator-1-8-secure-element-grp {
fsl,pins = <
/* v2x-secure-element power switch: io with pull-down */
IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x0000041
>;
};
se_pins: pinctrl-secure-element-grp {
fsl,pins = <
/* v2x-secure-element reset: io with pull-up */
IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x0000021
/*
* v2x-secure-element gpio0: io with pull-up
* pulled low by sxf after boot indicating ready for commands
*/
IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x0000021
/* v2x-secure-element gpio1: io with pull-up */
IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x0000021
>;
};
usdhc1_pins: pinctrl-usdhc1-grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000061
>;
};
usdhc2_pins: pinctrl-usdhc2-grp {
fsl,pins = <
IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000040
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
>;
};
};
&lpspi2 {
cs-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
num-cs = <1>;
pinctrl-0 = <&lpspi2_pins>, <&se_pins>;
pinctrl-names = "default";
status = "okay";
};
/* console */
&lpuart0 {
pinctrl-0 = <&lpuart0_pins>;
pinctrl-names = "default";
status = "okay";
};
/* gnss */
&lpuart2 {
pinctrl-0 = <&lpuart2_pins>, <&gnss_pins>;
pinctrl-names = "default";
status = "okay";
};
&lsio_gpio3 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "SXF_RST", "SXF_GPIO0", "SXF_GPIO1", "", "",
"", "", "", "", "", "", "", "";
};
&lsio_mu5 {
status = "okay";
};
/* OTG port for boot */
&usbotg1 {
adp-disable;
disable-over-current;
dr_mode = "peripheral";
hnp-disable;
power-active-high;
srp-disable;
status = "okay";
};
&usbphy1 {
status = "okay";
};
/* eMMC */
&usdhc1 {
bus-width = <8>;
cap-mmc-hw-reset;
non-removable;
no-sd;
no-sdio;
pinctrl-0 = <&usdhc1_pins>;
pinctrl-1 = <&usdhc1_pins>;
pinctrl-2 = <&usdhc1_pins>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&v_3_3>;
vqmmc-supply = <&v_1_8>;
status = "okay";
};
/* DSRC Radio */
&usdhc2 {
bus-width = <4>;
keep-power-in-suspend;
max-frequency = <40000000>;
non-removable;
no-sd;
pinctrl-0 = <&usdhc2_pins>, <&dsrc_pins>;
pinctrl-names = "default";
vmmc-supply = <&v_3_3>;
vqmmc-supply = <&v_1_8>;
status = "okay";
};

5
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -533,6 +533,7 @@ &pcie_phy {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
@ -559,6 +560,10 @@ &pcie0_ep {
status = "disabled";
};
&pcie0_port0 {
reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
};
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";

10
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
View File

@ -254,10 +254,6 @@ &pwm2 {
status = "okay";
};
&reg_nvcc_sd {
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@ -466,7 +462,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
@ -479,7 +475,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
@ -492,7 +488,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
};

7
arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
View File

@ -342,7 +342,6 @@ reg_nvcc_sd: LDO5 {
regulator-name = "NVCC_SD (LDO5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
};
};
@ -795,7 +794,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
>;
};
@ -808,7 +807,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
>;
};
@ -821,7 +820,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
>;
};

21
arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-zinnia.dts Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano
* https://www.toradex.com/products/carrier-board/zinnia-carrier-board
*/
/dts-v1/;
#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-nonwifi.dtsi"
#include "imx8mm-verdin-zinnia.dtsi"
/ {
model = "Toradex Verdin iMX8M Mini on Zinnia";
compatible = "toradex,verdin-imx8mm-nonwifi-zinnia",
"toradex,verdin-imx8mm-nonwifi",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
};

21
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-zinnia.dts Normal file
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@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano
* https://www.toradex.com/products/carrier-board/zinnia-carrier-board
*/
/dts-v1/;
#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-wifi.dtsi"
#include "imx8mm-verdin-zinnia.dtsi"
/ {
model = "Toradex Verdin iMX8M Mini WB on Zinnia";
compatible = "toradex,verdin-imx8mm-wifi-zinnia",
"toradex,verdin-imx8mm-wifi",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
};

383
arch/arm64/boot/dts/freescale/imx8mm-verdin-zinnia.dtsi Normal file
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@ -0,0 +1,383 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Common dtsi for Verdin IMX8MM SoM on Zinnia carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano
* https://www.toradex.com/products/carrier-board/zinnia-carrier-board
*/
#include <dt-bindings/leds/common.h>
/ {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_zinnia_leds>;
/* LED1 Red - SODIMM 48 - LED1_R */
led-0 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
};
/* LED1 Blue - SODIMM 46 - LED1_B */
led-1 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
};
/* LED3 Red - SODIMM 44 - LED3_R */
led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
};
/* LED3 Green - SODIMM 54 - LED3_G */
led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
};
/* LED3 Blue - SODIMM 36 - LED3_B */
led-4 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
};
/* LED4 Red - SODIMM 34 - LED4_R */
led-5 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <4>;
gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
};
/* LED4 Green - SODIMM 32 - LED4_G */
led-6 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <4>;
gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
};
/* LED4 Blue - SODIMM 30 - LED4_B */
led-7 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <4>;
gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
};
zinnia-1v8-voltage {
compatible = "voltage-divider";
full-ohms = <39000>; /* 12k + 27k */
/* Verdin ADC_4 */
io-channels = <&verdin_som_adc 4>;
output-ohms = <27000>;
};
zinnia-3v3-voltage {
compatible = "voltage-divider";
full-ohms = <54000>; /* 27k + 27k */
/* Verdin ADC_3 */
io-channels = <&verdin_som_adc 5>;
output-ohms = <27000>;
};
zinnia-5v-voltage {
compatible = "voltage-divider";
full-ohms = <39000>; /* 27k + 12k */
/* Verdin ADC_2 */
io-channels = <&verdin_som_adc 6>;
output-ohms = <12000>;
};
/* Zinnia Power Supply Input Voltage */
zinnia-input-voltage {
compatible = "voltage-divider";
full-ohms = <204700>; /* 200k + 4.7k */
/* Verdin ADC_1 */
io-channels = <&verdin_som_adc 7>;
output-ohms = <4700>;
};
};
/* Verdin SPI_1 */
&ecspi2 {
pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_uart3_cts_gpio>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <1>;
spi-max-frequency = <18500000>;
};
};
/* EEPROM on Zinnia */
&eeprom_carrier_board {
status = "okay";
};
/* Verdin ETH_1 */
&fec1 {
status = "okay";
};
&gpio1 {
gpio-line-names =
"DI2_RB", /* SODIMM 216 */ /* 0 */
"",
"",
"",
"",
"",
"",
"",
"DO3_EN", /* SODIMM 220 */
"DI3_EN", /* SODIMM 222 */
"", /* 10 */
"DI2_EN", /* SODIMM 218 */
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"";
};
&gpio2 {
gpio-line-names =
"", /* 0 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
""; /* 20 */
};
&gpio3 {
gpio-line-names =
"", /* 0 */
"",
"",
"",
"DO1_EN", /* SODIMM 206 */
"",
"DI3_RB", /* SODIMM 56 */
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"";
};
&gpio4 {
gpio-line-names =
"", /* 0 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"";
};
&gpio5 {
gpio-line-names =
"", /* 0 */
"",
"",
"",
"",
"DI1_EN", /* SODIMM 208 */
"",
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"",
"DI1_RB", /* SODIMM 210 */
"DO2_EN", /* SODIMM 212 */
"",
"";
};
/* Temperature sensor on Zinnia */
&hwmon_temp {
compatible = "ti,tmp1075";
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
};
/* Verdin UART_3 */
&uart1 {
status = "okay";
};
/* Verdin UART_1 */
&uart2 {
status = "okay";
};
/* Verdin UART_2 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_rts>;
rs485-rx-during-tx;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
/* Verdin USB_1 */
&usbotg1 {
status = "okay";
};
/* Verdin USB_2 */
&usbotg2 {
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>,
<&pinctrl_gpio2>,
<&pinctrl_gpio3>,
<&pinctrl_gpio4>,
<&pinctrl_gpio5>,
<&pinctrl_gpio6>,
<&pinctrl_gpio7>,
<&pinctrl_gpio8>,
<&pinctrl_qspi1_io0_gpio>;
pinctrl_qspi1_io0_gpio: gpio3io6grp {
fsl,pins = <MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x184>; /* SODIMM 56 */
};
pinctrl_uart3_cts_gpio: gpio5io9grp {
fsl,pins = <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x184>; /* SODIMM 143 */
};
pinctrl_zinnia_leds: zinnialedsgrp {
fsl,pins =
<MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x16>, /* SODIMM 30 */
<MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x16>, /* SODIMM 32 */
<MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x16>, /* SODIMM 34 */
<MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x16>, /* SODIMM 36 */
<MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x16>, /* SODIMM 44 */
<MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16>, /* SODIMM 46 */
<MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x16>, /* SODIMM 48 */
<MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x16>; /* SODIMM 54 */
};
};

16
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View File

@ -735,7 +735,7 @@ &uart2 {
/* Verdin UART_2 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_cts>, <&pinctrl_uart3_rts>;
uart-has-rtscts;
};
@ -1144,12 +1144,20 @@ pinctrl_uart2: uart2grp {
<MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
};
pinctrl_uart3_cts: uart3ctsgrp {
fsl,pins =
<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
};
pinctrl_uart3_rts: uart3rtsgrp {
fsl,pins =
<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>; /* SODIMM 141 */
};
pinctrl_uart3: uart3grp {
fsl,pins =
<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
<MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>; /* SODIMM 137 */
};
pinctrl_uart4: uart4grp {

11
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -1370,6 +1370,17 @@ pcie0: pcie@33800000 {
phys = <&pcie_phy>;
phy-names = "pcie-phy";
status = "disabled";
pcie0_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie0_ep: pcie-ep@33800000 {

2
arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts
View File

@ -112,7 +112,7 @@ &i2c3 {
&ifm_pmic {
interrupt-parent = <&gpio2>;
interrupts = <0 GPIO_ACTIVE_LOW>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&iomuxc {

2
arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts
View File

@ -99,7 +99,7 @@ &i2c3 {
&ifm_pmic {
interrupt-parent = <&gpio5>;
interrupts = <17 GPIO_ACTIVE_LOW>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
&iomuxc {

2
arch/arm64/boot/dts/freescale/imx8mp-ab2.dts
View File

@ -281,7 +281,7 @@ pca9450: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_pmic>;
regulators {

37
arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi Normal file
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@ -0,0 +1,37 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022-2026 Marek Vasut
*/
&display_bl {
pwms = <&pwm1 0 5000000 0>;
};
&i2c_dhpdk_panel {
#address-cells = <1>;
#size-cells = <0>;
touch_lvds: touchscreen@41 {
compatible = "ilitek,ili251x";
reg = <0x41>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <16384>;
touchscreen-size-y = <9600>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
&panel {
compatible = "chefree,ch101olhlwh-002";
};
&pwm1 {
status = "okay";
};

33
arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-clock.dtsi Normal file
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@ -0,0 +1,33 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024-2026 Marek Vasut
*/
#include <dt-bindings/clock/imx8mp-clock.h>
&media_blk_ctrl {
/*
* Sys PLL3 supplies TC9595 RefClk
* Audio PLL2 supplies MEDIA_DISP1_PIX (DSI)
* Video PLL1 supplies MEDIA_DISP2_PIX (LVDS)
*/
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
<&clk IMX8MP_AUDIO_PLL2>,
<&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_AUDIO_PLL2_OUT>,
<&clk IMX8MP_VIDEO_PLL1_OUT>;
assigned-clock-rates = <500000000>, <200000000>,
<0>, <0>, <0>, <0>;
};
&tc_bridge {
assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
<&clk IMX8MP_CLK_CLKOUT2>,
<&clk IMX8MP_SYS_PLL3_OUT>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>;
};

31
arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-common.dtsi Normal file
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@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp-dhcom-overlay-panel-clock.dtsi"
&{/} {
display_bl: display-bl {
compatible = "pwm-backlight";
brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
default-brightness-level = <8>;
enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */
status = "okay";
};
panel: panel {
backlight = <&display_bl>;
power-supply = <&reg_vdd_3p3v_awo>;
port {
panel_in: endpoint {
};
};
};
};

35
arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-dpi.dtsi Normal file
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@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022-2026 Marek Vasut
*/
#include "imx8mp-dhcom-overlay-panel-common.dtsi"
&lcdif1 {
status = "okay";
};
&mipi_dsi {
status = "okay";
};
&panel_in {
remote-endpoint = <&tc_bridge_out>;
};
&tc_bridge {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
tc_bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};

53
arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi Normal file
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@ -0,0 +1,53 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2022-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/imx8mp-clock.h>
#include "imx8mp-dhcom-overlay-panel-dpi.dtsi"
&{/} {
led {
led-0 {
/* LED5 GPIO conflicts with Touchscreen IRQ GPIO-E */
status = "disabled";
};
};
};
&i2c_dhpdk_panel {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dhcom_e>;
/* Touchscreen IRQ GPIO-E conflicts with LED5 GPIO */
interrupt-parent = <&gpio5>;
interrupts = <22 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
};
};
&display_bl {
pwms = <&pwm1 0 5000000 PWM_POLARITY_INVERTED>;
};
&mipi_dsi {
/*
* This is DSIM PLL frequency, DSI HS clock lane frequency
* is half of the "samsung,burst-clock-frequency" value.
*/
samsung,burst-clock-frequency = <500000000>;
};
&panel {
compatible = "edt,etm0700g0edh6";
};
&pwm1 {
status = "okay";
};

22
arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-lvds.dtsi Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
#include "imx8mp-dhcom-overlay-panel-common.dtsi"
&ldb_lvds_ch0 {
remote-endpoint = <&panel_in>;
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
status = "okay";
};
&panel_in {
remote-endpoint = <&ldb_lvds_ch0>;
};

10
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk-overlay-eth2xfast.dtso Normal file
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@ -0,0 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
&ethphypdk { /* Micrel KSZ9131RNXI */
status = "disabled";
};

40
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso Normal file
View File

@ -0,0 +1,40 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx8mp-dhcom-overlay-panel-lvds.dtsi"
#include "imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi"
&{/} {
gpio-keys {
button-1 {
/* BUTTON1 GPIO conflicts with Touchscreen RESET GPIO-B */
status = "disabled";
};
};
led {
led-2 {
/* LED7 GPIO conflicts with Touchscreen IRQ GPIO-H */
status = "disabled";
};
};
};
&media_blk_ctrl {
/*
* The Chefree CH101OLHLWH-002 panel requires 71.1 MHz LVDS clock.
* Set IMX8MP_VIDEO_PLL1 to 497.7 MHz , since 497.7 MHz / 7 = 71.1 MHz .
*/
assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <0>, <497700000>;
};
&touch_lvds {
pinctrl-0 = <&pinctrl_dhcom_b &pinctrl_dhcom_h>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
};

32
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x21.dtso Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2022-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
eeprom@0 {
compatible = "microchip,25aa010a", "atmel,at25";
reg = <0>;
address-width = <8>;
pagesize = <16>;
size = <128>;
spi-max-frequency = <5000000>;
};
};
&i2c5 {
#address-cells = <1>;
#size-cells = <0>;
eeprom@56 {
compatible = "atmel,24c04";
reg = <0x56>;
pagesize = <16>;
};
};

32
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-531-100-x22.dtso Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2022-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
eeprom@0 {
compatible = "microchip,25aa010a", "atmel,at25";
reg = <0>;
address-width = <8>;
pagesize = <16>;
size = <128>;
spi-max-frequency = <5000000>;
};
};
&i2c4 {
#address-cells = <1>;
#size-cells = <0>;
eeprom@56 {
compatible = "atmel,24c04";
reg = <0x56>;
pagesize = <16>;
};
};

25
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2-overlay-560-300-x12.dtso Normal file
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@ -0,0 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2022-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi"
#include "imx8mp-pinfunc.h"
&{/} {
led {
led-0 {
/* LED5 GPIO conflicts with Touchscreen IRQ GPIO-E */
status = "disabled";
};
};
};
&pinctrl_dhcom_e {
fsl,pins = <
/* GPIO_E */
MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x40000000
>;
};

2
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
View File

@ -152,7 +152,7 @@ codec_dai: simple-audio-card,codec {
};
};
&i2c5 {
i2c_dhpdk_panel: &i2c5 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;

53
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtso Normal file
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@ -0,0 +1,53 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx8mp-dhcom-overlay-panel-lvds.dtsi"
#include "imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi"
#include "imx8mp-pinfunc.h"
&{/} {
gpio-keys {
button-1 {
/* TA2 GPIO conflicts with Touchscreen RESET GPIO-B */
status = "disabled";
};
button-2 {
/* TA3 GPIO conflicts with Touchscreen IRQ GPIO-C */
status = "disabled";
};
};
led {
led-2 {
/* LED2 GPIO conflicts with BL-ON1 GPIO-G */
status = "disabled";
};
};
};
&media_blk_ctrl {
/*
* The Chefree CH101OLHLWH-002 panel requires 71.1 MHz LVDS clock.
* Set IMX8MP_VIDEO_PLL1 to 497.7 MHz , since 497.7 MHz / 7 = 71.1 MHz .
*/
assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <0>, <497700000>;
};
&pinctrl_dhcom_c {
fsl,pins = <
/* GPIO_C */
MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x40000000
>;
};
&touch_lvds {
pinctrl-0 = <&pinctrl_dhcom_b &pinctrl_dhcom_c>;
pinctrl-names = "default";
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
};

32
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x40.dtso Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
eeprom@0 {
compatible = "microchip,25aa010a", "atmel,at25";
reg = <0>;
address-width = <8>;
pagesize = <16>;
size = <128>;
spi-max-frequency = <5000000>;
};
};
&i2cmuxed0 {
#address-cells = <1>;
#size-cells = <0>;
eeprom@56 {
compatible = "atmel,24c04";
reg = <0x56>;
pagesize = <16>;
};
};

32
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-531-100-x41.dtso Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
eeprom@0 {
compatible = "microchip,25aa010a", "atmel,at25";
reg = <0>;
address-width = <8>;
pagesize = <16>;
size = <128>;
spi-max-frequency = <5000000>;
};
};
&i2c4 {
#address-cells = <1>;
#size-cells = <0>;
eeprom@56 {
compatible = "atmel,24c04";
reg = <0x56>;
pagesize = <16>;
};
};

24
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-560-300-x36.dtso Normal file
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@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi"
&{/} {
gpio-keys {
button-3 {
/* TA4 GPIO conflicts with Touchscreen IRQ GPIO-E */
status = "disabled";
};
};
led {
led-2 {
/* LED2 GPIO conflicts with BL-ON1 GPIO-G */
status = "disabled";
};
};
};

36
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-732-100-x36.dtso Normal file
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@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx8mp-dhcom-overlay-panel-clock.dtsi"
&lcdif1 {
status = "okay";
};
&mipi_dsi {
samsung,burst-clock-frequency = <1000000000>;
status = "okay";
};
&tc_bridge {
assigned-clock-rates = <26000000>, <26000000>, <416000000>;
toshiba,hpd-pin = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
reg = <2>;
endpoint {
toshiba,pre-emphasis = /bits/ 8 <1 1>;
};
};
};
};

56
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtso Normal file
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@ -0,0 +1,56 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/gpio/gpio.h>
/* This DTO requires HI00106 SoM variant. */
&{/} {
led {
led-0 {
/* LED0 GPIO conflicts with #SDIO_RST GPIO-D */
status = "disabled";
};
};
};
&uart3 {
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
assigned-clock-rates = <80000000>;
bluetooth {
compatible = "cypress,cyw4373a0-bt";
max-speed = <4000000>;
};
};
/* SD slot */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
broken-cd;
cap-power-off-card;
keep-power-in-suspend;
non-removable;
vmmc-supply = <&buck4>;
#address-cells = <1>;
#size-cells = <0>;
wifi@1 { /* muRata 2AE */
compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
reg = <1>;
/*
* The "host-wake" interrupt output is by default not
* connected to the SoC, but can be connected on to
* SoC pin on the carrier board.
*/
reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */
};
};

32
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtso Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi"
&mipi_csi_1 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipi_csi0_ep: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&ov5640 {
powerdown-gpios = <&csi2exp 1 GPIO_ACTIVE_HIGH>;
reset-gpios = <&csi2exp 0 GPIO_ACTIVE_LOW>;
};

32
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtso Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi"
&mipi_csi_0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipi_csi0_ep: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&ov5640 {
powerdown-gpios = <&csi2exp 2 GPIO_ACTIVE_HIGH>;
reset-gpios = <&csi2exp 3 GPIO_ACTIVE_LOW>;
};

64
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi Normal file
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@ -0,0 +1,64 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/gpio/gpio.h>
&{/} {
camera0_1v5_pwr: regulator-camera0-1v5 {
compatible = "regulator-fixed";
regulator-name = "camera0-1v5-reg";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
camera0_1v8_pwr: regulator-camera0-1v8 {
compatible = "regulator-fixed";
regulator-name = "camera0-1v8-reg";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
camera0_2v8_pwr: regulator-camera0-2v8 {
compatible = "regulator-fixed";
regulator-name = "camera0-2v8-reg";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
};
&i2cmuxed0 {
#address-cells = <1>;
#size-cells = <0>;
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk IMX8MP_CLK_CLKOUT1>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>,
<&clk IMX8MP_CLK_CLKOUT1>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>, <24000000>;
AVDD-supply = <&camera0_2v8_pwr>;
DOVDD-supply = <&camera0_1v8_pwr>;
DVDD-supply = <&camera0_1v5_pwr>;
port {
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi0_ep>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&isi_0 {
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
View File

@ -165,7 +165,7 @@ i2c-mux@70 {
#address-cells = <1>;
#size-cells = <0>;
i2cmuxed0: i2c@0 {
i2c_dhpdk_panel: i2cmuxed0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;

77
arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso Normal file
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@ -0,0 +1,77 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx8mp-dhcom-overlay-panel-dpi.dtsi"
#include "imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi"
#include "imx8mp-pinfunc.h"
&{/} {
lvds-encoder {
compatible = "onnn,fin3385", "lvds-encoder";
pclk-sample = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_bridge_in: endpoint {
remote-endpoint = <&tc_bridge_out>;
};
};
port@1 {
reg = <1>;
lvds_bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
};
&mipi_dsi {
/*
* This is DSIM PLL frequency, DSI HS clock lane frequency
* is half of the "samsung,burst-clock-frequency" value.
*/
samsung,burst-clock-frequency = <900000000>;
};
&panel_in {
remote-endpoint = <&lvds_bridge_out>;
};
&tc_bridge_out {
remote-endpoint = <&lvds_bridge_in>;
};
&touch_lvds {
pinctrl-0 = <&pinctrl_dhcom_b &pinctrl_dhcom_h>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
};
&iomuxc {
/*
* The following DHCOM GPIOs are used on this board.
* Therefore, they have been removed from the list below.
* B: Touch controller #RESET
* H: Touch controller IRQ
* I: Yellow led
*/
pinctrl-0 = <&pinctrl_dhcom_a &pinctrl_dhcom_c &pinctrl_dhcom_d
&pinctrl_dhcom_e &pinctrl_dhcom_f &pinctrl_dhcom_g
&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
&pinctrl_dhcom_s &pinctrl_dhcom_int>;
};

3
arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts
View File

@ -114,6 +114,9 @@ &hdmi_tx_phy {
status = "disabled";
};
i2c_dhpdk_panel: &i2c5 {
};
&irqsteer_hdmi {
status = "disabled";
};

85
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth1xfast.dtso Normal file
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@ -0,0 +1,85 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/imx8mp-clock.h>
&eqos { /* First ethernet */
pinctrl-0 = <&pinctrl_eqos_rmii>;
phy-handle = <&ethphy0f>;
phy-mode = "rmii";
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>;
};
&ethphy0g { /* Micrel KSZ9131RNXI */
status = "disabled";
};
&ethphy0f { /* SMSC LAN8740Ai */
status = "okay";
};
&fec { /* Second ethernet -- HS connector not populated on 1x RMII PHY SoM */
status = "disabled";
};
/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */
&hdmi_blk_ctrl {
status = "disabled";
};
&hdmi_pvi {
status = "disabled";
};
&hdmi_tx {
status = "disabled";
};
&hdmi_tx_phy {
status = "disabled";
};
&irqsteer_hdmi {
status = "disabled";
};
&lcdif3 {
status = "disabled";
};
&pcie_phy {
status = "disabled";
};
&pcie {
status = "disabled";
};
/* No WiFi/BT chipset on this SoM variant. */
&uart2 {
bluetooth {
status = "disabled";
};
};
&usb_dwc3_0 {
maximum-speed = "high-speed";
};
&usb_dwc3_1 {
maximum-speed = "high-speed";
};
/* No WiFi/BT chipset on this SoM variant. */
&usdhc1 {
status = "disabled";
};

29
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som-overlay-eth2xfast.dtso Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
#include "imx8mp-dhcom-som-overlay-eth1xfast.dtso"
/* Dual RMII 100/Full Fast ethernet on this SoM variant. */
&ethphy1f { /* SMSC LAN8740Ai */
status = "okay";
};
&fec { /* Second ethernet */
pinctrl-0 = <&pinctrl_fec_rmii>;
phy-handle = <&ethphy1f>;
phy-mode = "rmii";
status = "okay";
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;
};
/* Resistive touch controller not populated on this one SoM variant. */
&touch_som {
status = "disabled";
};

4
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
* Copyright (C) 2021-2026 Marek Vasut
*/
#include "imx8mp.dtsi"
@ -398,7 +398,7 @@ channel@7 { /* Voltage over AIN3 and GND. */
};
};
touchscreen@49 {
touch_som: touchscreen@49 {
compatible = "ti,tsc2004";
reg = <0x49>;
interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;

9
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -770,11 +770,12 @@ &pcie_phy {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie0>;
vpcie3v3aux-supply = <&reg_pcie0>;
supports-clkreq;
status = "okay";
status = "disabled";
};
&pcie0_ep {
@ -783,6 +784,10 @@ &pcie0_ep {
status = "disabled";
};
&pcie0_port0 {
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
@ -870,7 +875,7 @@ &uart3 {
status = "okay";
};
&usdhc1 {
m2_usdhc: &usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;

14
arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts
View File

@ -49,7 +49,9 @@ pwm-beeper {
reg_vcc_panel: regulator-vcc-panel {
compatible = "regulator-fixed";
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vcc_panel>;
gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
@ -63,7 +65,7 @@ &ecspi2 {
eeram@0 {
compatible = "microchip,48l640";
reg = <0>;
spi-max-frequency = <20000000>;
spi-max-frequency = <16000000>;
};
};
@ -172,7 +174,7 @@ &gpio4 {
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5>;
gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",
gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "VCC_PANEL_EN",
"PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1",
"CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",
"SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",
@ -329,4 +331,10 @@ MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x46 /* CAN_ADR0 */
MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x46 /* CAN_ADR1 */
>;
};
pinctrl_reg_vcc_panel: regvccpanelgrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x46
>;
};
};

7
arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi
View File

@ -311,7 +311,6 @@ reg_nvcc_sd: LDO5 {
regulator-name = "NVCC_SD (LDO5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
};
};
@ -815,7 +814,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0
>;
};
@ -827,7 +826,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0
>;
};
@ -839,7 +838,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0
>;
};

62
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
View File

@ -38,6 +38,18 @@ fan0: fan {
#cooling-cells = <2>;
};
hdmi-connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
panel_lvds1: panel-lvds1 {
/* compatible panel in overlay */
backlight = <&backlight_lvds1>;
@ -126,6 +138,13 @@ reg_vcc_1v8_exp_con: regulator-vcc-1v8 {
regulator-name = "VCC_1V8_EXP_CON";
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
model = "audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
};
thermal-zones {
soc-thermal {
trips {
@ -146,6 +165,10 @@ map1 {
};
};
&aud2htx {
status = "okay";
};
/* TPM */
&ecspi1 {
#address-cells = <1>;
@ -201,6 +224,32 @@ &flexcan2 {
status = "okay";
};
&hdmi_pai {
status = "okay";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
@ -244,6 +293,10 @@ &i2c3 {
scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&lcdif3 {
status = "okay";
};
&ldb_lvds_ch1 {
remote-endpoint = <&panel1_in>;
};
@ -444,6 +497,15 @@ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2

3
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
View File

@ -609,6 +609,9 @@ tlv320aic3x04: audio-codec@18 {
reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
iov-supply = <&reg_vcc_1v8>;
ldoin-supply = <&reg_vcc_3v3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
};
se97_1c: temperature-sensor@1c {

24
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso
View File

@ -17,6 +17,7 @@
panel {
compatible = "boe,av101hdt-a10";
backlight = <&backlight>;
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_panel>;
pinctrl-names = "default";
@ -40,7 +41,30 @@ reg_vbus: regulator-vbus {
};
};
&i2c4 {
#address-cells = <1>;
#size-cells = <0>;
backlight: backlight@6f {
compatible = "maxim,max25014";
reg = <0x6f>;
default-brightness = <50>;
enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
maxim,iset = <7>;
maxim,strings = <1 1 1 0>;
};
};
&iomuxc {
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04
(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_panel: panelgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07

19
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso
View File

@ -16,6 +16,7 @@
panel {
compatible = "boe,av123z7m-n17";
backlight = <&backlight>;
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_panel>;
pinctrl-names = "default";
@ -91,10 +92,26 @@ lvds1_out: endpoint {
};
};
/* max25014 @ 0x6f */
backlight: backlight@6f {
compatible = "maxim,max25014";
reg = <0x6f>;
default-brightness = <50>;
enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
maxim,iset = <7>;
maxim,strings = <1 1 1 1>;
};
};
&iomuxc {
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04
(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_lvds_bridge: lvdsbridgegrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14

21
arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-zinnia.dts Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
* https://www.toradex.com/products/carrier-board/zinnia-carrier-board
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-nonwifi.dtsi"
#include "imx8mp-verdin-zinnia.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus on Zinnia";
compatible = "toradex,verdin-imx8mp-nonwifi-zinnia",
"toradex,verdin-imx8mp-nonwifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

21
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-zinnia.dts Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
* https://www.toradex.com/products/carrier-board/zinnia-carrier-board
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-wifi.dtsi"
#include "imx8mp-verdin-zinnia.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus WB on Zinnia";
compatible = "toradex,verdin-imx8mp-wifi-zinnia",
"toradex,verdin-imx8mp-wifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

422
arch/arm64/boot/dts/freescale/imx8mp-verdin-zinnia.dtsi Normal file
View File

@ -0,0 +1,422 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Common dtsi for Verdin IMX8MP SoM on Zinnia carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
* https://www.toradex.com/products/carrier-board/zinnia-carrier-board
*/
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_zinnia_leds>;
/* LED1 Red - SODIMM 48 - LED1_R */
led-1 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
};
/* LED1 Blue - SODIMM 46 - LED1_B */
led-2 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio5 01 GPIO_ACTIVE_HIGH>;
};
/* LED3 Red - SODIMM 44 - LED3_R */
led-3 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
};
/* LED3 Green - SODIMM 54 - LED3_G */
led-4 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
};
/* LED3 Blue - SODIMM 36 - LED3_B */
led-5 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
};
/* LED4 Red - SODIMM 34 - LED4_R */
led-6 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <4>;
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
};
/* LED4 Green - SODIMM 32 - LED4_G */
led-7 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <4>;
gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
};
/* LED4 Blue - SODIMM 30 - LED4_B */
led-8 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <4>;
gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
};
};
zinnia-1v8-voltage {
compatible = "voltage-divider";
full-ohms = <39000>; /* 12k + 27k */
/* Verdin ADC_4 */
io-channels = <&verdin_som_adc 4>;
output-ohms = <27000>;
};
zinnia-3v3-voltage {
compatible = "voltage-divider";
full-ohms = <54000>; /* 27k + 27k */
/* Verdin ADC_3 */
io-channels = <&verdin_som_adc 5>;
output-ohms = <27000>;
};
zinnia-5v-voltage {
compatible = "voltage-divider";
full-ohms = <39000>; /* 27k + 12k */
/* Verdin ADC_2 */
io-channels = <&verdin_som_adc 6>;
output-ohms = <12000>;
};
/* Zinnia Power Supply Input Voltage */
zinnia-input-voltage {
compatible = "voltage-divider";
full-ohms = <204700>; /* 200k + 4.7k */
/* Verdin ADC_1 */
io-channels = <&verdin_som_adc 7>;
output-ohms = <4700>;
};
};
/* Verdin SPI_1 */
&ecspi1 {
pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_uart2_cts_gpio>;
cs-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>, <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <1>;
spi-max-frequency = <18500000>;
};
};
/* EEPROM on Zinnia */
&eeprom_carrier_board {
status = "okay";
};
/* Verdin ETH_1 */
&eqos {
status = "okay";
};
/* Verdin ETH_2 */
&fec {
phy-handle = <&ethphy2>;
phy-mode = "rgmii-id";
status = "okay";
};
&verdin_eth2_mdio {
ethphy2: ethernet-phy@2 {
reg = <2>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
};
};
/* Verdin CAN_1 */
&flexcan1 {
status = "okay";
};
&gpio1 {
gpio-line-names =
"DO1_EN", /* 0 */ /* SODIMM 206 */
"DI1_EN", /* SODIMM 208 */
"",
"",
"",
"DI1_RB", /* SODIMM 210 */
"DO2_EN", /* SODIMM 212 */
"DI2_RB", /* SODIMM 216 */
"DI2_EN", /* SODIMM 218 */
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"",
"",
"",
"",
"";
};
&gpio2 {
gpio-line-names =
"", /* 0 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
""; /* 20 */
};
&gpio3 {
gpio-line-names =
"", /* 0 */
"",
"",
"",
"",
"",
"DI3_RB", /* SODIMM 56 */
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"",
"",
"",
"",
"";
};
&gpio4 {
gpio-line-names =
"", /* 0 */
"DI3_EN", /* SODIMM 222 */
"",
"DO3_EN", /* SODIMM 220 */
"",
"",
"",
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 30 */
"";
};
&gpio5 {
gpio-line-names =
"", /* 0 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"",
"",
"",
"",
"";
};
/* Temperature sensor on Zinnia */
&hwmon_temp {
compatible = "ti,tmp1075";
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
};
/* Verdin UART_1 */
&uart1 {
status = "okay";
};
/* Verdin UART_2 */
&uart2 {
pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart2_rts>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
status = "okay";
};
/* Verdin UART_3 */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usb3_0 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
/* Verdin USB_2 */
&usb3_1 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>,
<&pinctrl_gpio2>,
<&pinctrl_gpio3>,
<&pinctrl_gpio4>,
<&pinctrl_gpio5>,
<&pinctrl_gpio6>,
<&pinctrl_gpio7>,
<&pinctrl_gpio8>,
<&pinctrl_qspi1_io0_gpio>;
pinctrl_uart2_cts_gpio: gpio2io6grp {
fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x184>; /* SODIMM 143 */
};
pinctrl_qspi1_io0_gpio: gpio3io6grp {
fsl,pins = <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x184>; /* SODIMM 56 */
};
pinctrl_zinnia_leds: zinnialedsgrp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x16>, /* SODIMM 30 */
<MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x16>, /* SODIMM 32 */
<MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x16>, /* SODIMM 34 */
<MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x16>, /* SODIMM 36 */
<MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x16>, /* SODIMM 44 */
<MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x16>, /* SODIMM 46 */
<MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x16>, /* SODIMM 48 */
<MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x16>; /* SODIMM 54 */
};
};

14
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
View File

@ -846,7 +846,7 @@ &uart1 {
/* Verdin UART_2 */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart2_cts>, <&pinctrl_uart2_rts>;
uart-has-rtscts;
};
@ -1277,10 +1277,18 @@ pinctrl_uart1: uart1grp {
<MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */
};
pinctrl_uart2_cts: uart2ctsgrp {
fsl,pins =
<MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>; /* SODIMM 143 */
};
pinctrl_uart2_rts: uart2rtsgrp {
fsl,pins =
<MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>; /* SODIMM 141 */
};
pinctrl_uart2: uart2grp {
fsl,pins =
<MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */
<MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */
<MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */
<MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */
};

11
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -2265,6 +2265,17 @@ pcie0: pcie: pcie@33800000 {
phys = <&pcie_phy>;
phy-names = "pcie-phy";
status = "disabled";
pcie0_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie0_ep: pcie_ep: pcie-ep@33800000 {

10
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -369,6 +369,7 @@ mipi_dsi_out: endpoint {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&pcie0_refclk>,
@ -389,9 +390,14 @@ &pcie0_ep {
status = "disabled";
};
&pcie0_port0 {
reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&pcie0_refclk>,
@ -414,6 +420,10 @@ &pcie1_ep {
status = "disabled";
};
&pcie1_port0 {
reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};

22
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -1768,6 +1768,17 @@ pcie0: pcie@33800000 {
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
status = "disabled";
pcie0_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie0_ep: pcie-ep@33800000 {
@ -1846,6 +1857,17 @@ pcie1: pcie@33c00000 {
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
status = "disabled";
pcie1_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie1_ep: pcie-ep@33c00000 {

10
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@ -810,6 +810,7 @@ &pciea {
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pciea>;
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pciea>;
vpcie3v3aux-supply = <&reg_pciea>;
@ -817,15 +818,24 @@ &pciea {
status = "okay";
};
&pciea_port0 {
reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
};
&pcieb {
phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
status = "disabled";
};
&pcieb_port0 {
reset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
};
&qm_pwm_lvds0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_lvds0>;

22
arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
View File

@ -41,6 +41,17 @@ pcie0: pciea: pcie@5f000000 {
power-domains = <&pd IMX_SC_R_PCIE_A>;
fsl,max-link-speed = <3>;
status = "disabled";
pciea_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie0_ep: pciea_ep: pcie-ep@5f000000 {
@ -91,6 +102,17 @@ pcie1: pcieb: pcie@5f010000 {
power-domains = <&pd IMX_SC_R_PCIE_B>;
fsl,max-link-speed = <3>;
status = "disabled";
pcieb_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
sata: sata@5f020000 {

871
arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts Normal file
View File

@ -0,0 +1,871 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2019-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8qm-tqma8qm.dtsi"
/ {
model = "TQ-Systems i.MX8QM TQMa8QM on MBa8x";
compatible = "tq,imx8qm-tqma8qm-mba8x", "tq,imx8qm-tqma8qm", "fsl,imx8qm";
adc {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>;
};
aliases {
rtc0 = &pcf85063;
rtc1 = &rtc;
};
chosen {
stdout-path = &lpuart0;
};
clk_xtal25: clk-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
autorepeat;
switch-1 {
label = "SWITCH_A";
linux,code = <BTN_0>;
gpios = <&lsio_gpio2 11 GPIO_ACTIVE_LOW>;
wakeup-source;
};
switch-2 {
label = "SWITCH_B";
linux,code = <BTN_1>;
gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpioled>;
user-led0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
user-led1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
fan0: pwm-fan {
compatible = "pwm-fan";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwmfan>;
fan-supply = <&reg_pwm_fan>;
#cooling-cells = <2>;
/* typical 25 kHz -> 40.000 nsec */
pwms = <&lsio_pwm3 0 40000 PWM_POLARITY_INVERTED>;
cooling-levels = <0 32 64 128 196 240>;
pulses-per-revolution = <2>;
interrupt-parent = <&lsio_gpio2>;
interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
status = "disabled";
};
reg_mba8x_12v: regulator-mba8x-12v {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_mba8x_12v>;
regulator-name = "MBa8x-V12";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&lsio_gpio1 2 GPIO_ACTIVE_HIGH>;
};
reg_mba8x_v3v3: regulator-mba8x-v3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_pwm_fan: regulator-pwm-fan {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regpwmfan>;
regulator-name = "FAN_PWR";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&lsio_gpio2 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_mba8x_12v>;
};
reg_usb_phy: regulator-usb-phy {
compatible = "regulator-fixed";
regulator-max-microvolt = <3000000>;
regulator-min-microvolt = <3000000>;
regulator-name = "usb-phy-dummy";
};
reg_v1v5_pcie: regulator-v1v5-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_pcie_v1v5>;
regulator-name = "V_1V5_MPCIE";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
vin-supply = <&reg_mba8x_v3v3>;
enable-active-high;
gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
regulator-always-on;
};
reg_v1v8: regulator-v1v8 {
compatible = "regulator-fixed";
regulator-name = "MBa8x-V1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_v3v3_pcie: regulator-v3v3-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_pcie_v3v3>;
regulator-name = "V_3V3_MPCIE";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_mba8x_v3v3>;
enable-active-high;
gpio = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>;
regulator-always-on;
};
reg_v3v3_sd: regulator-v3v3-sd {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_v3v3_sd>;
regulator-name = "V3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_mba8x_v3v3>;
gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
off-on-delay-us = <200000>;
};
reg_vref_v1v8: regulator-vref-v1v8 {
compatible = "regulator-fixed";
regulator-name = "VREF_V1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* global autoconfigured region for contiguous allocations
* must not exceed memory size and region
*/
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x3c000000>;
alloc-ranges = <0 0x96000000 0 0x3c000000>;
linux,cma-default;
};
decoder_boot: decoder-boot@84000000 {
reg = <0 0x84000000 0 0x2000000>;
no-map;
};
encoder1_boot: encoder1-boot@86000000 {
reg = <0 0x86000000 0 0x200000>;
no-map;
};
encoder2_boot: encoder2-boot@86200000 {
reg = <0 0x86200000 0 0x200000>;
no-map;
};
decoder_rpc: decoder-rpc@92000000 {
reg = <0 0x92000000 0 0x100000>;
no-map;
};
encoder1_rpc: encoder1-rpc@92100000 {
reg = <0 0x92100000 0 0x700000>;
no-map;
};
encoder2_rpc: encoder1-rpc@92800000 {
reg = <0 0x92800000 0 0x700000>;
no-map;
};
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "tqm-tlv320aic32";
ssi-controller = <&sai1>;
audio-codec = <&tlv320aic3x04>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
model = "imx-audio-dp";
audio-cpu = <&sai5>;
hdmi-out;
};
thermal-zones {
cpu0-thermal {
trips {
soc_active0_0: trip-active0 {
temperature = <40000>;
hysteresis = <5000>;
type = "active";
};
soc_active0_1: trip-active1 {
temperature = <48000>;
hysteresis = <3000>;
type = "active";
};
soc_active0_2: trip-active2 {
temperature = <60000>;
hysteresis = <10000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&soc_active0_0>;
cooling-device = <&fan0 1 1>;
};
map2 {
trip = <&soc_active0_1>;
cooling-device = <&fan0 2 2>;
};
map3 {
trip = <&soc_active0_2>;
cooling-device = <&fan0 3 3>;
};
};
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
nvmem-cells = <&fec_mac0>;
nvmem-cell-names = "mac-address";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ethphy0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
reset-gpios = <&lsio_gpio2 6 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
interrupt-parent = <&lsio_gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy3>;
nvmem-cells = <&fec_mac1>;
nvmem-cell-names = "mac-address";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ethphy3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
reset-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&hsio_phy {
fsl,hsio-cfg = "pciea-pcieb-sata";
fsl,refclk-pad-mode = "input";
status = "okay";
};
/* no refclock gating */
&hsio_refa_clk {
compatible = "fixed-factor-clock";
clocks = <&pcieclk 0>;
clock-div = <1>;
clock-mult = <1>;
/delete-property/ enable-gpios;
};
&hsio_refb_clk {
compatible = "fixed-factor-clock";
clocks = <&pcieclk 0>;
clock-div = <1>;
clock-mult = <1>;
/delete-property/ enable-gpios;
};
&i2c1 {
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
ldoin-supply = <&reg_mba8x_v3v3>;
iov-supply = <&reg_v1v8>;
};
sensor1: temperature-sensor@1c {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1c>;
};
eeprom2: eeprom@54 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x54>;
pagesize = <16>;
vcc-supply = <&reg_mba8x_v3v3>;
};
pcieclk: clock-generator@68 {
compatible = "renesas,9fgv0441";
reg = <0x68>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
&lpspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>, <&lsio_gpio3 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&lpspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>;
cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>, <&lsio_gpio3 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
&lpspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>, <&lsio_gpio3 11 GPIO_ACTIVE_LOW>;
status = "okay";
};
&lpuart0 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&lpuart1 {
/* X62 pin header */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&lpuart2 {
/* mikroBUS */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
&lsio_gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio2>;
gpio-line-names = "", "", "", "",
"", "PCIE0_DISABLE#", "", "";
pcie0-wdisable1-hog {
gpio-hog;
gpios = <5 0>;
output-high;
line-name = "PCIE0_DISABLE#";
};
pcie-clk-pd-hog {
gpio-hog;
gpios = <10 0>;
output-high;
line-name = "PCIE_CLK_PD#";
};
};
&lsio_pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lsio_pwm3>;
status = "okay";
};
&pciea {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pciea>;
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcieb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>;
phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy";
reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
status = "okay";
};
&sai5 {
status = "okay";
};
&sai5_lpcg {
status = "okay";
};
&sata {
status = "okay";
};
&usbphy1 {
phy-3p0-supply = <&reg_usb_phy>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
over-current-active-low;
dr_mode = "otg";
status = "okay";
};
&usb3_phy {
status = "okay";
};
&usbotg3 {
/* over-current disabled by default */
status = "okay";
};
&usbotg3_cdns3 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhub>;
status = "okay";
hub_2_0: hub@1 {
compatible = "usb451,8142";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&lsio_gpio2 7 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_mba8x_v3v3>;
};
hub_3_0: hub@2 {
compatible = "usb451,8140";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&lsio_gpio2 7 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_mba8x_v3v3>;
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_v3v3_sd>;
no-mmc;
no-sdio;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio>;
pinctrl_adc0: adc0grp {
fsl,pins = <IMX8QM_ADC_IN1_DMA_ADC0_IN1 0x02000060>,
<IMX8QM_ADC_IN2_DMA_ADC0_IN2 0x02000060>;
};
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 0x00000041>,
<IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021>;
};
pinctrl_ethphy3: ethphy3grp {
fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000041>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
<IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000041>,
<IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>,
<IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000041>,
<IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000041>,
<IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000041>,
<IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000041>,
<IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000041>,
<IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000041>,
<IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>,
<IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>,
<IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>,
<IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>,
<IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>,
<IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0>,
<IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000041>,
<IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000041>,
<IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000041>,
<IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000041>,
<IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000041>,
<IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000041>,
<IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000041>,
<IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000041>,
<IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000040>,
<IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000040>,
<IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000040>,
<IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000040>,
<IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000040>,
<IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000040>;
};
pinctrl_flexcan1: flexcan0grp {
fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021>,
<IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021>;
};
pinctrl_flexcan2: flexcan1grp {
fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021>,
<IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021>;
};
pinctrl_gpio2: gpio2grp {
fsl,pins = <IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000021>,
<IMX8QM_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 0x00000021>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = /* GPIO0_05 on X62:26 */
<IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021>,
/* GPIO1_14 on X64:21 */
<IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 0x00000021>,
/* GPIO1_15 on X64:23 */
<IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 0x00000021>,
/* GPIO2_17 on X63:37 */
<IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021>,
/* GPIO2_21 on X63:39 */
<IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 0x00000021>,
/* GPIO4_12 on X61:24 */
<IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021>,
/* GPIO4_11 on X61:26 */
<IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021>,
/* GPIO4_10 on X61:28 */
<IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 0x00000021>,
/* GPIO4_09 on X61:30 */
<IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021>,
/* GPIO5_23 on X62:24 */
<IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021>,
/* GPIO5_24 on X61:15 */
<IMX8QM_USDHC2_CLK_LSIO_GPIO5_IO24 0x00000021>,
/* GPIO5_25 on X61:17 */
<IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x00000021>,
/* GPIO5_26 on X61:19 */
<IMX8QM_USDHC2_DATA0_LSIO_GPIO5_IO26 0x00000021>,
/* GPIO5_27 on X61:21 */
<IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x00000021>,
/* GPIO5_28 on X61:23 */
<IMX8QM_USDHC2_DATA2_LSIO_GPIO5_IO28 0x00000021>,
/* GPIO5_29 on X61:25 */
<IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x00000021>;
};
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 0x00000021>,
<IMX8QM_SCU_GPIO0_04_LSIO_GPIO1_IO00 0x00000021>;
};
pinctrl_gpioled: gpioledgrp {
fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>,
<IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x00000021>;
};
pinctrl_lpspi0_cs: lpspi0csgrp {
fsl,pins = <IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x00000021>,
<IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021>;
};
pinctrl_lpspi0: lpspi0grp {
fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x0600004d>,
<IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x0600004d>,
<IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x0600004d>;
};
pinctrl_lpspi1_cs: lpspi1csgrp {
fsl,pins = <IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021>,
<IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 0x00000021>;
};
pinctrl_lpspi1: lpspi1grp {
fsl,pins = <IMX8QM_ADC_IN3_DMA_SPI1_SCK 0x0600004d>,
<IMX8QM_ADC_IN4_DMA_SPI1_SDO 0x0600004d>,
<IMX8QM_ADC_IN5_DMA_SPI1_SDI 0x0600004d>;
};
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004d>,
<IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004d>,
<IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004d>;
};
pinctrl_lpspi2_cs: lpspi2sgrp {
fsl,pins = <IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x00000021>,
<IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX 0x06000021>,
<IMX8QM_UART0_TX_DMA_UART0_TX 0x06000021>,
<IMX8QM_UART0_CTS_B_DMA_UART0_CTS_B 0x00000021>,
<IMX8QM_UART0_RTS_B_DMA_UART0_RTS_B 0x00000021>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX 0x06000021>,
<IMX8QM_UART1_TX_DMA_UART1_TX 0x06000021>,
<IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x00000021>,
<IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x00000021>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000021>,
<IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000021>;
};
pinctrl_lsio_pwm3: lsiopwm3grp {
fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT 0x00000021>;
};
pinctrl_pciea: pcieagrp {
fsl,pins = <IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021>,
<IMX8QM_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000021>,
<IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021>;
};
pinctrl_pcieb: pciebgrp {
fsl,pins = <IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021>,
<IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021>,
<IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021>;
};
pinctrl_pwmfan: pwmfangrp {
fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 0x30>;
};
pinctrl_reg_mba8x_12v: regmba12vgrp {
fsl,pins = <IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000021>;
};
pinctrl_reg_pcie_v1v5: regpcie1v5grp {
fsl,pins = <IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x00000021>;
};
pinctrl_reg_pcie_v3v3: regpcie3v3grp {
fsl,pins = <IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021>;
};
pinctrl_regpwmfan: regpwmfangrp {
fsl,pins = <IMX8QM_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 0x00000021>;
};
pinctrl_reg_v3v3_sd: regv3v3sdgrp {
fsl,pins = <IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000041>,
<IMX8QM_SAI1_RXC_AUD_SAI1_RXC 0x06000041>,
<IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS 0x06000041>,
<IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000061>,
<IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000041>,
<IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004d>;
};
pinctrl_usbhub: usbhubgrp {
fsl,pins = <IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>,
<IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
<IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
<IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
<IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
<IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
<IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
<IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
<IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
<IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
<IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
<IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
<IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
<IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
<IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
<IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
<IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
<IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
<IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
<IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins = <IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021>,
<IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021>;
};
};

325
arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi Normal file
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@ -0,0 +1,325 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2019-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8qm.dtsi"
/ {
model = "TQ-Systems i.MX8QM TQMa8QM";
compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm";
/* Due to missing workaround for ERR050104 */
cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
/delete-node/ cpu@101;
};
memory@80000000 {
device_type = "memory";
/*
* DRAM base addr, size : 1024 MiB DRAM
* should be corrected by bootloader
*/
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reg_tqma8x_v3v3: regulator-tqma8x-v3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
/* SW7 controlled by SCU */
reg_1v8_io1: regulator-v1v8-io1 {
compatible = "regulator-fixed";
regulator-name = "V_1V8_IO1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
/* LDO4 controlled by SCU */
reg_3v3_emmc: regulator-v3v3-emmc {
compatible = "regulator-fixed";
regulator-name = "V_3V3_EMMC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&acm {
status = "okay";
};
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0>;
vref-supply = <&reg_vref_v1v8>;
status = "okay";
};
/* TQMa8QM only uses industrial grade, reduce trip points accordingly */
&cpu_alert0 {
temperature = <95000>;
};
&cpu_crit0 {
temperature = <100000>;
};
&cpu_alert1 {
temperature = <95000>;
};
&cpu_crit1 {
temperature = <100000>;
};
&gpu_alert0 {
temperature = <95000>;
};
&gpu_crit0 {
temperature = <100000>;
};
&gpu_alert1 {
temperature = <95000>;
};
&gpu_crit1 {
temperature = <100000>;
};
&drc_alert0 {
temperature = <95000>;
};
&drc_crit0 {
temperature = <100000>;
};
/* end of temperature grade adjustments */
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <66000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
vcc-supply = <&reg_1v8_io1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1gpio>;
scl-gpios = <&lsio_gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&lsio_gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
se97: temperature-sensor@1b {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1b>;
};
pcf85063: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
quartz-load-femtofarads = <7000>;
};
at24c02: eeprom@53 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
read-only;
vcc-supply = <&reg_tqma8x_v3v3>;
};
m24c64: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_tqma8x_v3v3>;
};
};
&mu_m0 {
status = "okay";
};
&mu1_m0 {
status = "okay";
};
&mu2_m0 {
status = "okay";
};
&thermal_zones {
/delete-node/ cpu1-thermal;
pmic0-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device =
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
vmmc-supply = <&reg_3v3_emmc>;
vqmmc-supply = <&reg_1v8_io1>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&vpu {
compatible = "nxp,imx8qm-vpu";
status = "okay";
};
&vpu_core0 {
memory-region = <&decoder_boot>, <&decoder_rpc>;
status = "okay";
};
&vpu_core1 {
memory-region = <&encoder1_boot>, <&encoder1_rpc>;
status = "okay";
};
&vpu_core2 {
memory-region = <&encoder2_boot>, <&encoder2_rpc>;
status = "okay";
};
&iomuxc {
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004d>,
<IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004d>;
};
pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
fsl,pins = <IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0x0600004d>,
<IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0x0600004d>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>,
<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>,
<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>,
<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0000004d>,
<IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0000004d>,
<IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0000004d>,
<IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0000004d>,
<IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0000004d>,
<IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0000004d>,
<IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0000004d>,
<IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0000004d>,
<IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0000004d>,
<IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0000004d>,
<IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0000004d>,
<IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0000004d>,
<IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0000004d>,
<IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0000004d>,
<IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0000004d>,
<IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0000004d>;
};
};

6
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -730,6 +730,7 @@ &pcie0 {
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcieb>;
vpcie3v3aux-supply = <&reg_pcieb>;
@ -742,10 +743,13 @@ &pcie0_ep {
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
vpcie-supply = <&reg_pcieb>;
status = "disabled";
};
&pcieb_port0 {
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
};
&scu_key {
status = "okay";
};

4
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
View File

@ -166,7 +166,7 @@ &lpi2c7 {
ptn5150_1: typec@1d {
compatible = "nxp,ptn5150";
reg = <0x1d>;
int-gpios = <&gpiof 3 IRQ_TYPE_EDGE_FALLING>;
int-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
status = "disabled";
@ -182,7 +182,7 @@ pcal6408: gpio@21 {
ptn5150_2: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
int-gpios = <&gpiof 5 IRQ_TYPE_EDGE_FALLING>;
int-gpios = <&gpiof 5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec2>;
status = "disabled";

67
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@ -302,6 +302,7 @@ wdog3: watchdog@292a0000 {
assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
timeout-sec = <40>;
bootph-all;
};
cgc1: clock-controller@292c0000 {
@ -858,6 +859,72 @@ spdif: spdif@2dab0000 {
dma-names = "rx", "tx";
status = "disabled";
};
isi: isi@2dac0000 {
compatible = "fsl,imx8ulp-isi";
reg = <0x2dac0000 0x10000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc5 IMX8ULP_CLK_ISI>,
<&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>;
clock-names = "axi", "apb";
power-domains = <&scmi_devpd IMX8ULP_PD_ISI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
isi_in: endpoint {
remote-endpoint = <&mipi_csi_out>;
};
};
};
};
mipi_csi: csi@2daf0000 {
compatible = "fsl,imx8ulp-mipi-csi2";
reg = <0x2daf0000 0x10000>,
<0x2dad0000 0x10000>;
clocks = <&pcc5 IMX8ULP_CLK_CSI>,
<&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>,
<&pcc5 IMX8ULP_CLK_CSI_CLK_UI>,
<&pcc5 IMX8ULP_CLK_CSI_REGS>;
clock-names = "core", "esc", "ui", "pclk";
assigned-clocks = <&pcc5 IMX8ULP_CLK_CSI>,
<&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>,
<&pcc5 IMX8ULP_CLK_CSI_CLK_UI>,
<&pcc5 IMX8ULP_CLK_CSI_REGS>;
assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>,
<&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>,
<&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>;
assigned-clock-rates = <200000000>,
<80000000>,
<100000000>,
<79200000>;
power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_CSI>;
resets = <&pcc5 5>, /* PCC5_CSI_REGS_SWRST */
<&pcc5 6>; /* PCC5_CSI_SWRST> */
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_csi_out: endpoint {
remote-endpoint = <&isi_in>;
};
};
};
};
};
gpiod: gpio@2e200000 {

4
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
View File

@ -631,12 +631,12 @@ pinctrl_adc0: adc0grp {
*/
pinctrl_atmel_adap: atmeladaptergrp {
fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21>, /* SODIMM 30 */
<IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021>; /* SODIMM 28 */
<IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x40000021>; /* SODIMM 28 */
};
/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
pinctrl_atmel_conn: atmelconnectorgrp {
fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021>, /* SODIMM 107 */
fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x40000021>, /* SODIMM 107 */
<IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21>; /* SODIMM 106 */
};

15
arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
View File

@ -195,10 +195,12 @@ mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,clkout-disable;
};
};
@ -220,6 +222,9 @@ mdio {
ethphy2: ethernet-phy@2 {
reg = <2>;
reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,clkout-disable;
};
};
@ -587,6 +592,8 @@ &usdhc3 {
};
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
@ -948,4 +955,10 @@ MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};

93
arch/arm64/boot/dts/freescale/imx91-93-phyboard-segin-peb-av-18.dtsi Normal file
View File

@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2026 PHYTEC Messtechnik GmbH
*
* Author: Florijan Plohl <florijan.plohl@norik.com>
*/
#include <dt-bindings/clock/imx93-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/dts-v1/;
/plugin/;
&{/} {
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <5>;
power-supply = <&reg_vcc_3v3_con>;
pwms = <&pwm7 0 5000000 0>;
};
panel {
compatible = "powertip,ph800480t032-zhc19";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel>;
backlight = <&backlight>;
enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_vcc_3v3_con>;
port {
panel_in: endpoint {
remote-endpoint = <&dpi_to_panel>;
};
};
};
pwm7: pwm-7 {
compatible = "pwm-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
#pwm-cells = <3>;
};
reg_vcc_3v3_con: regulator-vcc-3v3-con {
compatible = "regulator-fixed";
regulator-name = "VCC3V3_CON";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
};
};
&dpi_bridge {
status = "okay";
};
&dpi_to_panel {
remote-endpoint = <&panel_in>;
bus-width = <18>;
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>;
assigned-clock-rates = <27272728>;
status = "okay";
};
&lpi2c2 {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@41 {
compatible = "ilitek,ili2130";
reg = <0x41>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreen>;
interrupt-parent = <&gpio4>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
wakeup-source;
};
};
&media_blk_ctrl {
status = "okay";
};

435
arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts Normal file
View File

@ -0,0 +1,435 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx91.dtsi"
/ {
compatible = "fsl,imx91-9x9-qsb", "fsl,imx91";
model = "NXP i.MX91 9x9 Quick Start Board";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &bbnsm_rtc;
serial0 = &lpuart1;
};
chosen {
stdout-path = &lpuart1;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
off-on-delay-us = <12000>;
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x10000000>;
linux,cma-default;
};
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&eqos {
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-names = "default";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,clkout-disable;
};
};
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-names = "default";
status = "okay";
p3t1085: temperature-sensor@48 {
compatible = "nxp,p3t1085";
reg = <0x48>;
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
typec1_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <15000000>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
interrupt-parent = <&pcal6524>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
};
};
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-names = "default";
status = "okay";
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
pinctrl-0 = <&pinctrl_pcal6524>;
pinctrl-names = "default";
};
pmic@32 {
compatible = "nxp,pf9453";
reg = <0x32>;
interrupt-parent = <&pcal6524>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1140000>;
regulator-min-microvolt = <1060000>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <610000>;
regulator-ramp-delay = <12500>;
};
buck3: BUCK3 {
regulator-name = "BUCK3";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3450000>;
regulator-min-microvolt = <1650000>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3450000>;
regulator-min-microvolt = <1650000>;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1650000>;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1890000>;
regulator-min-microvolt = <760000>;
};
ldo_snvs: LDO-SNVS {
regulator-name = "LDO-SNVS";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1650000>;
};
};
};
};
&lpuart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
};
&usbotg1 {
adp-disable;
disable-over-current;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usdhc1 {
bus-width = <8>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
fsl,tuning-step = <1>;
status = "okay";
};
&usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&reg_usdhc2_vmmc>;
fsl,tuning-step = <1>;
status = "okay";
};
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};

57
arch/arm64/boot/dts/freescale/imx91-phyboard-segin-peb-av-18.dtso Normal file
View File

@ -0,0 +1,57 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2026 PHYTEC Messtechnik GmbH
*
* Author: Florijan Plohl <florijan.plohl@norik.com>
*/
#include "imx91-pinfunc.h"
#include "imx91-93-phyboard-segin-peb-av-18.dtsi"
&iomuxc {
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x57e
MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x51e
MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x51e
MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x51e
MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x51e
MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x51e
MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x51e
MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x51e
MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x51e
MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x51e
MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x51e
MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x51e
MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x51e
MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x51e
MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x51e
MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x51e
MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x51e
MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x51e
MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x51e
MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x51e
MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x51e
MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x51e
>;
};
pinctrl_panel: panelgrp {
fsl,pins = <
MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x1133e
>;
};
pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x1133e
>;
};
pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x11e
MX91_PAD_ENET1_RD2__GPIO4_IO12 0x1133e
>;
};
};

24
arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
View File

@ -137,6 +137,24 @@ ethphy2: ethernet-phy@2 {
};
};
&gpio1 {
gpio-line-names = "", "USER_LED", "I2C1_SCL", "I2C1_SDA";
};
&gpio3 {
gpio-line-names = "SD1_nCD", "", "", "", "",
"", "", "SD1_nRESET";
};
&gpio4 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "CAN_EN", "", "", "",
"", "", "", "RESET_PHY", "",
"", "RTC_nINT", "PMIC_IRQ_B";
};
/* CAN */
&flexcan1 {
pinctrl-names = "default";
@ -309,7 +327,7 @@ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CLK__USDHC2_CLK 0x118e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1386
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
@ -321,7 +339,7 @@ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX91_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
@ -333,7 +351,7 @@ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CLK__USDHC2_CLK 0x118e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x139e

39
arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi
View File

@ -8,6 +8,7 @@
*/
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/nxp,pca9450-regulator.h>
#include "imx91.dtsi"
@ -88,6 +89,28 @@ ethphy1: ethernet-phy@1 {
};
};
&gpio1 {
gpio-line-names = "", "USER_LED";
};
&gpio2 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "I2C3_SDA", "I2C3_SCL";
};
&gpio4 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "RESET_PHY", "",
"", "", "PMIC_IRQ_B";
};
/* I2C3 */
&lpi2c3 {
clock-frequency = <400000>;
@ -138,6 +161,7 @@ buck5: BUCK5 {
regulator-min-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-initial-mode = <PCA9450_BUCK_MODE_FORCE_PWM>;
};
buck6: BUCK6 {
@ -192,6 +216,7 @@ &usdhc1 {
bus-width = <8>;
non-removable;
no-1-8-v;
fsl,strobe-dll-delay-target = <1>;
status = "okay";
};
@ -218,7 +243,7 @@ MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x50e
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x50e
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x50e
MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x4000050e
MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX91_PAD_ENET2_RXC__GPIO4_IO23 0x502
>;
};
@ -250,7 +275,7 @@ MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x179e
MX91_PAD_SD1_CLK__USDHC1_CLK 0x119e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1386
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
@ -260,13 +285,13 @@ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX91_PAD_SD1_CLK__USDHC1_CLK 0x11be
MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x139e
@ -276,13 +301,13 @@ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x139e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x139e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x139e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x139e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX91_PAD_SD1_CLK__USDHC1_CLK 0x11be
MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x139e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13be
@ -292,7 +317,7 @@ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13be
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13be
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13be
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13be
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};

9
arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
View File

@ -90,6 +90,13 @@ reg_vref_1v8: regulator-adc-vref {
regulator-max-microvolt = <1800000>;
};
reg_rgb_sel: regulator-rgb-enable {
compatible = "regulator-fixed";
regulator-name = "RGBSEL";
gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -195,6 +202,7 @@ pca6408_1: gpio@20 {
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
vcc-supply = <&reg_rgb_sel>;
};
pca6408_2: gpio@21 {
@ -204,6 +212,7 @@ pca6408_2: gpio@21 {
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
vcc-supply = <&reg_rgb_sel>;
};
pca9534: gpio@22 {

527
arch/arm64/boot/dts/freescale/imx91-var-som-symphony.dts Normal file
View File

@ -0,0 +1,527 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Variscite Symphony carrier board for VAR-SOM-MX91
*
* Link: https://variscite.com/carrier-boards/symphony-board/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx91-var-som.dtsi"
/{
model = "Variscite VAR-SOM-MX91 on Symphony evaluation board";
compatible = "variscite,var-som-mx91-symphony",
"variscite,var-som-mx91", "fsl,imx91";
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &pca9534;
gpio5 = &pca6408;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
};
chosen {
stdout-path = &lpuart1;
};
gpio-keys {
compatible = "gpio-keys";
key-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
key-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
key-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
};
gpio-leds {
compatible = "gpio-leds";
led-hearthbeat {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
/*
* Needed only for Symphony <= v1.5
*/
reg_fec_phy: regulator-fec-phy {
compatible = "regulator-fixed";
regulator-name = "fec-phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <20000>;
gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6408 6 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
ele_reserved: ele-reserved@87de0000 {
compatible = "shared-dma-pool";
reg = <0 0x87de0000 0 0x100000>;
no-map;
};
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x40000000>;
reusable;
size = <0 0x10000000>;
linux,cma-default;
};
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
/* Use external instead of internal RTC*/
&bbnsm_rtc {
status = "disabled";
};
&eqos {
mdio {
ethphy1: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <5>;
eee-broken-1000t;
reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
vddio-supply = <&vddio1>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
vddio1: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
&ethphy0 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec_phy>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
pca9534: gpio@20 {
compatible = "nxp,pca9534";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9534>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
pca6408: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca6408>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
tpm-enable-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "tpm_en";
};
/* RGB_SEL */
lvds-brg-enable-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "lvds_brg_en";
};
};
/* USB Type-C Controller */
ptn5150: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_NONE>;
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&pca6408>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
};
/* DS1337 RTC module */
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
/* pins conflict */
&lpspi8 {
status = "disabled";
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&tpm4 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_tpm4>;
pinctrl-1 = <&pinctrl_tpm4_sleep>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
bus-width = <4>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
/* Watchdog */
&wdog3 {
status = "okay";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e
MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e
MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX91_PAD_PDM_CLK__CAN1_TX 0x139e
MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
fsl,pins = <
MX91_PAD_I2C1_SCL__GPIO1_IO0 0x31e
MX91_PAD_I2C1_SDA__GPIO1_IO1 0x31e
>;
};
pinctrl_pca6408: pca6408grp {
fsl,pins = <
MX91_PAD_GPIO_IO04__GPIO2_IO4 0x31e
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_tpm4: tpm4grp {
fsl,pins = <
MX91_PAD_GPIO_IO05__TPM4_CH0 0x51e
>;
};
pinctrl_tpm4_sleep: tpm4sleepgrp {
fsl,pins = <
MX91_PAD_GPIO_IO05__GPIO2_IO5 0x51e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_sleep: usdhc2sleep-grp {
fsl,pins = <
MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
>;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleep-grp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
>;
};
};

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arch/arm64/boot/dts/freescale/imx91-var-som.dtsi Normal file
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@ -0,0 +1,456 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common dtsi for Variscite VAR-SOM-MX91
*
* Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/var-som-mx91/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include "imx91.dtsi"
/{
model = "Variscite VAR-SOM-MX91 module";
compatible = "variscite,var-som-mx91", "fsl,imx91";
usdhc3_pwrseq: mmc-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
simple-audio-card,mclk-fs = <256>;
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
};
};
&eqos {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
snps,clk-csr = <5>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
eee-broken-1000t;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <2237500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&clk IMX93_CLK_SAI1_GATE>;
clock-names = "mclk";
AVDD-supply = <&buck5>;
CPVDD-supply = <&buck5>;
DBVDD-supply = <&buck4>;
DCVDD-supply = <&buck5>;
MICVDD-supply = <&buck5>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
};
&lpspi8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi8>;
cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* BT module */
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart5>, <&pinctrl_bluetooth>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&sai1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-1 = <&pinctrl_sai1_sleep>;
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
/* WiFi */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
bus-width = <4>;
keep-power-in-suspend;
mmc-pwrseq = <&usdhc3_pwrseq>;
non-removable;
wakeup-source;
status = "okay";
};
&iomuxc {
pinctrl_bluetooth: bluetoothgrp {
fsl,pins = <
MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e
>;
};
pinctrl_eqos_sleep: eqos-sleepgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp {
fsl,pins = <
MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e
MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e
>;
};
pinctrl_lpspi8: lpspi8grp {
fsl,pins = <
MX91_PAD_GPIO_IO12__GPIO2_IO12 0x31e
MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x31e
MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e
MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x31e
>;
};
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e
MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e
MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e
MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e
MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e
>;
};
pinctrl_sai1_sleep: sai1-sleepgrp {
fsl,pins = <
MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e
MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e
MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e
MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e
MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e
MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e
MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
pinctrl_usdhc3_wlan: usdhc3-wlangrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x51e
>;
};
};

3
arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
View File

@ -525,6 +525,7 @@ wdog3: watchdog@42490000 {
clocks = <&clk IMX93_CLK_WDOG3_GATE>;
timeout-sec = <40>;
status = "disabled";
bootph-all;
};
wdog4: watchdog@424a0000 {
@ -534,6 +535,7 @@ wdog4: watchdog@424a0000 {
clocks = <&clk IMX93_CLK_WDOG4_GATE>;
timeout-sec = <40>;
status = "disabled";
bootph-all;
};
wdog5: watchdog@424b0000 {
@ -543,6 +545,7 @@ wdog5: watchdog@424b0000 {
clocks = <&clk IMX93_CLK_WDOG5_GATE>;
timeout-sec = <40>;
status = "disabled";
bootph-all;
};
tpm3: pwm@424e0000 {

1
arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi
View File

@ -187,7 +187,6 @@ mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;

110
arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi Normal file
View File

@ -0,0 +1,110 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx93-pinfunc.h"
&{/} {
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
};
panel {
compatible = "ontat,kd50g21-40nt-a1";
backlight = <&backlight>;
power-supply = <&reg_rpi_3v3>;
port {
panel_in: endpoint {
remote-endpoint = <&dpi_to_panel>;
};
};
};
};
&dpi_bridge {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dpi_to_panel: endpoint {
remote-endpoint = <&panel_in>;
bus-width = <18>;
};
};
};
};
&iomuxc {
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e
MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e
MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e
MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e
MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e
MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e
MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e
MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e
MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e
MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e
MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e
MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e
MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e
MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e
MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e
MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e
MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e
MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e
MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e
MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e
MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e
MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e
>;
};
};
&lcdif {
status = "okay";
};
&media_blk_ctrl {
status = "okay";
};
&pcal6524 {
/*
* exp-sel-hog has property 'output-low' while DT overlay doesn't
* support /delete-property/. Both 'output-low' and 'output-high'
* will exist under hog nodes if DT overlay file sets 'output-high'.
* Workaround is to disable this hog and create new hog with
* 'output-high'.
*/
exp-sel-hog {
status = "disabled";
};
exp-high-sel-hog {
gpio-hog;
gpios = <22 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&sai3 {
/* disable due to GPIO12 and GPIO17~20 pin conflicts with LCDIF */
status = "disabled";
};

106
arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso
View File

@ -3,108 +3,4 @@
* Copyright 2026 NXP
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx93-pinfunc.h"
&{/} {
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
};
panel {
compatible = "ontat,kd50g21-40nt-a1";
backlight = <&backlight>;
power-supply = <&reg_rpi_3v3>;
port {
panel_in: endpoint {
remote-endpoint = <&dpi_to_panel>;
};
};
};
};
&dpi_bridge {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dpi_to_panel: endpoint {
remote-endpoint = <&panel_in>;
bus-width = <18>;
};
};
};
};
&iomuxc {
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e
MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e
MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e
MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e
MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e
MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e
MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e
MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e
MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e
MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e
MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e
MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e
MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e
MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e
MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e
MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e
MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e
MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e
MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e
MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e
MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e
MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e
>;
};
};
&lcdif {
status = "okay";
};
&media_blk_ctrl {
status = "okay";
};
&pcal6524 {
/*
* exp-sel-hog has property 'output-low' while DT overlay doesn't
* support /delete-property/. Both 'output-low' and 'output-high'
* will exist under hog nodes if DT overlay file sets 'output-high'.
* Workaround is to disable this hog and create new hog with
* 'output-high'.
*/
exp-sel-hog {
status = "disabled";
};
exp-high-sel-hog {
gpio-hog;
gpios = <22 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&sai3 {
/* disable due to GPIO12 and GPIO17~20 pin conflicts with LCDIF */
status = "disabled";
};
#include "imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi"

14
arch/arm64/boot/dts/freescale/imx93-9x9-qsb-tianma-tm050rdh03.dtso Normal file
View File

@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
#include <dt-bindings/gpio/gpio.h>
#include "imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtsi"
&{/} {
panel {
compatible = "tianma,tm050rdh03";
enable-gpios = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
};
};

1
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
View File

@ -228,7 +228,6 @@ mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";

39
arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
View File

@ -141,6 +141,37 @@ &flexcan1 {
status = "okay";
};
&gpio1 {
gpio-line-names = "", "USER_LED", "I2C2_SCL", "I2C2_SDA";
};
&gpio2 {
gpio-line-names = "SPI6_CS0", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "TPM_nIRQ", "", "",
"", "", "", "", "",
"", "", "", "I2C3_SDA", "I2C3_SCL";
};
&gpio3 {
gpio-line-names = "SD2_nCD", "", "", "", "",
"", "", "SD2_nRESET", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "nENET1_INT";
};
&gpio4 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "nCAN_EN", "", "", "",
"", "", "", "RESET_PHY", "",
"", "RTC_nINT", "PMIC_IRQ_B";
};
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
@ -339,8 +370,8 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000178e
MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001386
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001386
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001386
@ -352,7 +383,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
@ -365,7 +396,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e

57
arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-18.dtso Normal file
View File

@ -0,0 +1,57 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2026 PHYTEC Messtechnik GmbH
*
* Author: Florijan Plohl <florijan.plohl@norik.com>
*/
#include "imx93-pinfunc.h"
#include "imx91-93-phyboard-segin-peb-av-18.dtsi"
&iomuxc {
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x57e
MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x51e
MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x51e
MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x51e
MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x51e
MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x51e
MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x51e
MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x51e
MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x51e
MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x51e
MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x51e
MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x51e
MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x51e
MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x51e
MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x51e
MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x51e
MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x51e
MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x51e
MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x51e
MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x51e
MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x51e
MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x51e
>;
};
pinctrl_panel: panelgrp {
fsl,pins = <
MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1133e
>;
};
pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x1133e
>;
};
pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x11e
MX93_PAD_ENET1_RD2__GPIO4_IO12 0x1133e
>;
};
};

24
arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
View File

@ -145,6 +145,24 @@ &flexcan1 {
status = "okay";
};
&gpio1 {
gpio-line-names = "", "USER_LED", "I2C1_SCL", "I2C1_SDA";
};
&gpio3 {
gpio-line-names = "SD1_nCD", "", "", "", "",
"", "", "SD1_nRESET";
};
&gpio4 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "CAN_EN", "", "", "",
"", "", "", "RESET_PHY", "",
"", "RTC_nINT", "PMIC_IRQ_B";
};
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
@ -310,7 +328,7 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
@ -323,7 +341,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
@ -336,7 +354,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX93_PAD_SD2_CLK__USDHC2_CLK 0x118e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e

39
arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
View File

@ -9,6 +9,7 @@
*/
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/nxp,pca9450-regulator.h>
#include "imx93.dtsi"
@ -90,6 +91,28 @@ ethphy1: ethernet-phy@1 {
};
};
&gpio1 {
gpio-line-names = "", "USER_LED";
};
&gpio2 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "I2C3_SDA", "I2C3_SCL";
};
&gpio4 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "", "", "RESET_PHY", "",
"", "", "PMIC_IRQ_B";
};
/* I2C3 */
&lpi2c3 {
clock-frequency = <400000>;
@ -140,6 +163,7 @@ buck5: BUCK5 {
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-initial-mode = <PCA9450_BUCK_MODE_FORCE_PWM>;
};
buck6: BUCK6 {
@ -194,6 +218,7 @@ &usdhc1 {
bus-width = <8>;
non-removable;
no-1-8-v;
fsl,strobe-dll-delay-target = <1>;
status = "okay";
};
@ -220,7 +245,7 @@ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e
MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e
MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX93_PAD_ENET2_RXC__GPIO4_IO23 0x502
>;
};
@ -253,7 +278,7 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e
MX93_PAD_SD1_CLK__USDHC1_CLK 0x119e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386
@ -263,14 +288,14 @@ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX93_PAD_SD1_CLK__USDHC1_CLK 0x11be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
@ -280,14 +305,14 @@ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
MX93_PAD_SD1_CLK__USDHC1_CLK 0x11be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
@ -297,7 +322,7 @@ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};

654
arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts Normal file
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@ -0,0 +1,654 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Variscite Sonata carrier board for DART-MX93
*
* Link: https://variscite.com/carrier-boards/sonata-board/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx93-var-dart.dtsi"
/ {
model = "Variscite DART-MX93 on Sonata-Board";
compatible = "variscite,var-dart-mx93-sonata",
"variscite,var-dart-mx93",
"fsl,imx93";
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
serial6 = &lpuart7;
};
chosen {
stdout-path = &lpuart1;
};
gpio-keys {
compatible = "gpio-keys";
button-home {
label = "Home";
linux,code = <KEY_HOME>;
gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-up {
label = "Up";
linux,code = <KEY_UP>;
gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-down {
label = "Down";
linux,code = <KEY_DOWN>;
gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-back {
label = "Back";
linux,code = <KEY_BACK>;
gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds_gpio>;
led-emmc {
gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
label = "eMMC";
linux,default-trigger = "mmc0";
};
};
clk40m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "can_osc";
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VDD_SD2_3V3";
off-on-delay-us = <20000>;
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ethosu_mem: ethosu-region@88000000 {
compatible = "shared-dma-pool";
reusable;
reg = <0x0 0x88000000 0x0 0x8000000>;
};
vdev0vring0: vdev0vring0@87ee0000 {
reg = <0 0x87ee0000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@87ee8000 {
reg = <0 0x87ee8000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@87ef0000 {
reg = <0 0x87ef0000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@87ef8000 {
reg = <0 0x87ef8000 0 0x8000>;
no-map;
};
rsc_table: rsc-table@2021e000 {
reg = <0 0x2021e000 0 0x1000>;
no-map;
};
vdevbuffer: vdevbuffer@87f00000 {
compatible = "shared-dma-pool";
reg = <0 0x87f00000 0 0x100000>;
no-map;
};
ele_reserved: ele-reserved@87de0000 {
compatible = "shared-dma-pool";
reg = <0 0x87de0000 0 0x100000>;
no-map;
};
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
/* Use external instead of internal RTC */
&bbnsm_rtc {
status = "disabled";
};
&eqos {
mdio {
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
};
};
&ethphy0 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
pinctrl-names = "default", "sleep", "gpio";
scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pca9534: gpio@22 {
compatible = "nxp,pca9534";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_captouch>;
pinctrl-names = "default";
reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
touchscreen-inverted-x;
touchscreen-inverted-y;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
wakeup-source;
};
/* USB Type-C Controller */
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
interrupt-parent = <&gpio4>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&pinctrl_extcon>;
pinctrl-names = "default";
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
interrupt-parent = <&gpio2>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
wakeup-source;
};
};
&lpi2c5 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c5>;
pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
pinctrl-2 = <&pinctrl_lpi2c5_gpio>;
scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&lpi2c7 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c7>;
pinctrl-1 = <&pinctrl_lpi2c7_gpio>;
pinctrl-2 = <&pinctrl_lpi2c7_gpio>;
scl-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pca6408_1: gpio@20 {
compatible = "nxp,pcal6408";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
pca6408_2: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
};
};
&lpspi8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi8>;
cs-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
status = "okay";
/* CAN controller */
can0: can@0 {
compatible = "microchip,mcp251xfd";
reg = <0>;
clocks = <&clk40m>;
interrupt-parent = <&gpio2>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
spi-max-frequency = <1000000>;
};
};
/* Console (J10) */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Header (J12.4, J12.6) */
&lpuart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
status = "okay";
};
/* Header (J12.11, J12.13) */
&lpuart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7>;
status = "okay";
};
&tpm3 {
pinctrl-0 = <&pinctrl_tpm3>;
pinctrl-names = "default";
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-sdio;
no-mmc;
status = "okay";
};
&wdog3 {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_can: cangrp {
fsl,pins = <
MX93_PAD_GPIO_IO03__GPIO2_IO03 0x31e
>;
};
pinctrl_captouch: captouchgrp {
fsl,pins = <
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
pinctrl_extcon: extcongrp {
fsl,pins = <
MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x37e
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX93_PAD_PDM_CLK__CAN1_TX 0x139e
MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* GPIO Expanders shared IRQ */
MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
>;
};
pinctrl_leds_gpio: ledgrp {
fsl,pins = <
MX93_PAD_GPIO_IO11__GPIO2_IO11 0x31e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp {
fsl,pins = <
MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
>;
};
pinctrl_lpi2c5_gpio: lpi2c5-gpiogrp {
fsl,pins = <
MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x40000b9e
MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x40000b9e
>;
};
pinctrl_lpi2c7_gpio: lpi2c7-gpiogrp {
fsl,pins = <
MX93_PAD_GPIO_IO07__GPIO2_IO07 0x31e
MX93_PAD_GPIO_IO06__GPIO2_IO06 0x31e
>;
};
pinctrl_lpspi8: lpspi8grp {
fsl,pins = <
MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e
MX93_PAD_GPIO_IO01__GPIO2_IO01 0x31e
MX93_PAD_GPIO_IO12__GPIO2_IO12 0x31e
MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x31e
MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e
MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX93_PAD_GPIO_IO02__GPIO2_IO02 0x31e
>;
};
pinctrl_tpm3: tpm3grp {
fsl,pins = <
MX93_PAD_GPIO_IO24__TPM3_CH3 0x51e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e
MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e
MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
};

461
arch/arm64/boot/dts/freescale/imx93-var-dart.dtsi Normal file
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@ -0,0 +1,461 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common dtsi for Variscite DART-MX93
*
* Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-93/dart-mx93/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx93.dtsi"
/ {
model = "Variscite DART-MX93 Module";
compatible = "variscite,var-dart-mx93", "fsl,imx93";
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
};
&cm33 {
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu1 0 1>,
<&mu1 1 1>,
<&mu1 3 1>;
memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
status = "okay";
};
&eqos {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
snps,clk-csr = <5>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
};
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&clk IMX93_CLK_SAI1_GATE>;
clock-names = "mclk";
AVDD-supply = <&buck5>;
CPVDD-supply = <&buck5>;
DBVDD-supply = <&buck4>;
DCVDD-supply = <&buck5>;
MICVDD-supply = <&buck5>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
/* DMIC is connected to IN1L */
wlf,in1l-as-dmicdat1;
};
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <2237500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
/* BT module */
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&mu1 {
status = "okay";
};
&mu2 {
status = "okay";
};
&sai1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-1 = <&pinctrl_sai1_sleep>;
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
/* WiFi */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
mmc-pwrseq = <&wifi_pwrseq>;
keep-power-in-suspend;
bus-width = <4>;
non-removable;
wakeup-source;
status = "okay";
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
>;
};
pinctrl_eqos_sleep: eqos-sleepgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
fsl,pins = <
MX93_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e
MX93_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e
MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e
MX93_PAD_UART2_RXD__SAI1_MCLK 0x31e
>;
};
pinctrl_sai1_sleep: sai1-sleepgrp {
fsl,pins = <
MX93_PAD_SAI1_TXC__GPIO1_IO12 0x31e
MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x31e
MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x31e
MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x31e
MX93_PAD_UART2_RXD__GPIO1_IO06 0x31e
MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e
MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582
MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e
MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe
MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe
>;
};
pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__GPIO3_IO20 0x400
MX93_PAD_SD3_CMD__GPIO3_IO21 0x400
MX93_PAD_SD3_DATA0__GPIO3_IO22 0x400
MX93_PAD_SD3_DATA1__GPIO3_IO23 0x400
MX93_PAD_SD3_DATA2__GPIO3_IO24 0x400
MX93_PAD_SD3_DATA3__GPIO3_IO25 0x400
>;
};
pinctrl_usdhc3_wlan: usdhc3wlangrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x51e
>;
};
};

61
arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts
View File

@ -35,6 +35,7 @@ aliases {
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
serial6 = &lpuart7;
};
@ -158,6 +159,11 @@ led-0 {
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
/* Use external instead of internal RTC*/
&bbnsm_rtc {
status = "disabled";
@ -208,6 +214,29 @@ &lpi2c1 {
sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
pcal6408: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
status = "okay";
/* RGB_SEL */
lvds-brg-enable-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds_brg_en";
};
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
label = "tpm";
reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5206";
@ -290,6 +319,19 @@ &lpuart6 {
status = "okay";
};
&lpuart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7>;
status = "okay";
};
&tpm3 {
pinctrl-0 = <&pinctrl_tpm3>;
pinctrl-1 = <&pinctrl_tpm3_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@ -412,6 +454,18 @@ MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
>;
};
pinctrl_tpm3: tpm3grp {
fsl,pins = <
MX93_PAD_GPIO_IO24__TPM3_CH3 0x51e
>;
};
pinctrl_tpm3_sleep: tpm3sleepgrp {
fsl,pins = <
MX93_PAD_GPIO_IO24__GPIO2_IO24 0x51e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
@ -426,6 +480,13 @@ MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e
MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e

102
arch/arm64/boot/dts/freescale/imx94.dtsi
View File

@ -67,6 +67,13 @@ sai4_mclk: clock-sai4-mclk1 {
clock-output-names = "sai4_mclk";
};
clk_sys100m: clock-sys100m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "clk_sys100m";
};
firmware {
scmi {
compatible = "arm,scmi";
@ -1283,7 +1290,27 @@ wdog3: watchdog@49220000 {
timeout-sec = <40>;
fsl,ext-reset-output;
status = "disabled";
bootph-all;
};
wdog4: watchdog@49230000 {
compatible = "fsl,imx94-wdt", "fsl,imx93-wdt";
reg = <0x49230000 0x10000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>;
timeout-sec = <40>;
fsl,ext-reset-output;
status = "disabled";
bootph-all;
};
};
hsio_blk_ctl: syscon@4c0100c0 {
compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
reg = <0x0 0x4c0100c0 0x0 0x1>;
#clock-cells = <1>;
clocks = <&clk_sys100m>;
power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
};
usb3: usb@4c100000 {
@ -1340,6 +1367,79 @@ usbmisc: usbmisc@4c200200 {
#index-cells = <1>;
};
pcie0: pcie@4c300000 {
compatible = "fsl,imx94-pcie", "fsl,imx95-pcie";
reg = <0 0x4c300000 0 0x10000>,
<0 0x60100000 0 0xfe00000>,
<0 0x4c360000 0 0x10000>,
<0 0x4c340000 0 0x4000>;
reg-names = "dbi", "config", "atu", "app";
ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
<0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
linux,pci-domain = <2>;
msi-map = <0x0 &its 0x10 0x1>,
<0x100 &its 0x11 0x7>;
msi-map-mask = <0x1ff>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
num-viewport = <8>;
interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi", "dma";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic 0 0 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic 0 0 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic 0 0 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk IMX94_CLK_HSIO>,
<&scmi_clk IMX94_CLK_HSIOPLL>,
<&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
<&hsio_blk_ctl 0>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX94_CLK_HSIOPLL>,
<&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
fsl,max-link-speed = <3>;
status = "disabled";
};
pcie0_ep: pcie-ep@4c300000 {
compatible = "fsl,imx94-pcie-ep", "fsl,imx95-pcie-ep";
reg = <0 0x4c300000 0 0x10000>,
<0 0x4c360000 0 0x1000>,
<0 0x4c320000 0 0x1000>,
<0 0x4c340000 0 0x4000>,
<0 0x4c370000 0 0x10000>,
<0x9 0 1 0>;
reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
num-lanes = <1>;
interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
clocks = <&scmi_clk IMX94_CLK_HSIO>,
<&scmi_clk IMX94_CLK_HSIOPLL>,
<&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX94_CLK_HSIOPLL>,
<&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
msi-map = <0x0 &its 0x10 0x1>;
power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
status = "disabled";
};
netc_blk_ctrl: system-controller@4ceb0000 {
compatible = "nxp,imx94-netc-blk-ctrl";
reg = <0x0 0x4ceb0000 0x0 0x10000>,
@ -1481,7 +1581,7 @@ netc_emdio: mdio@18,0 {
ddr-pmu@4e090dc0 {
compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu";
reg = <0x0 0x4e090dc0 0x0 0x200>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
};
};
};

15
arch/arm64/boot/dts/freescale/imx943-evk-sdwifi.dtso Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
/dts-v1/;
/plugin/;
&pcie0 {
status = "disabled";
};
&usdhc3 {
status = "okay";
};

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