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clk: qcom: camcc-sm8450: Add SM8475 support
Add support to the SM8475 camera clock controller by extending the SM8450 camera clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240818204348.197788-11-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Danila Tikhonov
Bjorn Andersson
parent
f7f4afdd9f
commit
b815ccf5bf
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@ -857,7 +857,7 @@ config SM_CAMCC_8450
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depends on ARM64 || COMPILE_TEST
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select SM_GCC_8450
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help
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Support for the camera clock controller on SM8450 devices.
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Support for the camera clock controller on SM8450 or SM8475 devices.
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Say Y if you want to support camera devices and camera functionality.
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config SM_CAMCC_8550
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@ -54,6 +54,10 @@ static const struct pll_vco rivian_evo_vco[] = {
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{ 864000000, 1056000000, 0 },
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};
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static const struct pll_vco rivian_ole_vco[] = {
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{ 864000000, 1075000000, 0 },
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};
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static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
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static const struct alpha_pll_config cam_cc_pll0_config = {
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@ -66,6 +70,20 @@ static const struct alpha_pll_config cam_cc_pll0_config = {
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_cam_cc_pll0_config = {
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.l = 0x3e,
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.alpha = 0x8000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00008400,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll cam_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_evo_vco,
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@ -86,6 +104,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
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{ }
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};
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static struct clk_init_data sm8475_cam_cc_pll0_out_even_init = {
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.name = "cam_cc_pll0_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
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.offset = 0x0,
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.post_div_shift = 10,
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@ -109,6 +137,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
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{ }
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};
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static struct clk_init_data sm8475_cam_cc_pll0_out_odd_init = {
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.name = "cam_cc_pll0_out_odd",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
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.offset = 0x0,
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.post_div_shift = 14,
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@ -137,6 +175,20 @@ static const struct alpha_pll_config cam_cc_pll1_config = {
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_cam_cc_pll1_config = {
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.l = 0x25,
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.alpha = 0xeaaa,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll cam_cc_pll1 = {
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.offset = 0x1000,
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.vco_table = lucid_evo_vco,
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@ -157,6 +209,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
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{ }
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};
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static struct clk_init_data sm8475_cam_cc_pll1_out_even_init = {
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.name = "cam_cc_pll1_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll1.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
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.offset = 0x1000,
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.post_div_shift = 10,
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@ -183,6 +245,16 @@ static const struct alpha_pll_config cam_cc_pll2_config = {
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.config_ctl_hi1_val = 0x00000217,
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};
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static const struct alpha_pll_config sm8475_cam_cc_pll2_config = {
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.l = 0x32,
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.alpha = 0x0,
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.config_ctl_val = 0x10000030,
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.config_ctl_hi_val = 0x80890263,
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.config_ctl_hi1_val = 0x00000217,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00000000,
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};
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static struct clk_alpha_pll cam_cc_pll2 = {
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.offset = 0x2000,
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.vco_table = rivian_evo_vco,
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@ -208,6 +280,20 @@ static const struct alpha_pll_config cam_cc_pll3_config = {
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_cam_cc_pll3_config = {
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.l = 0x2d,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll cam_cc_pll3 = {
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.offset = 0x3000,
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.vco_table = lucid_evo_vco,
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@ -228,6 +314,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
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{ }
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};
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static struct clk_init_data sm8475_cam_cc_pll3_out_even_init = {
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.name = "cam_cc_pll3_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll3.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
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.offset = 0x3000,
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.post_div_shift = 10,
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@ -256,6 +352,20 @@ static const struct alpha_pll_config cam_cc_pll4_config = {
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_cam_cc_pll4_config = {
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.l = 0x2d,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll cam_cc_pll4 = {
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.offset = 0x4000,
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.vco_table = lucid_evo_vco,
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@ -276,6 +386,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
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{ }
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};
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static struct clk_init_data sm8475_cam_cc_pll4_out_even_init = {
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.name = "cam_cc_pll4_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll4.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
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.offset = 0x4000,
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.post_div_shift = 10,
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@ -304,6 +424,20 @@ static const struct alpha_pll_config cam_cc_pll5_config = {
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_cam_cc_pll5_config = {
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.l = 0x2d,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll cam_cc_pll5 = {
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.offset = 0x5000,
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.vco_table = lucid_evo_vco,
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@ -324,6 +458,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
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{ }
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};
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static struct clk_init_data sm8475_cam_cc_pll5_out_even_init = {
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.name = "cam_cc_pll5_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll5.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
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.offset = 0x5000,
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.post_div_shift = 10,
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@ -352,6 +496,20 @@ static const struct alpha_pll_config cam_cc_pll6_config = {
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_cam_cc_pll6_config = {
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.l = 0x2d,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll cam_cc_pll6 = {
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.offset = 0x6000,
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.vco_table = lucid_evo_vco,
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@ -372,6 +530,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
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{ }
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};
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static struct clk_init_data sm8475_cam_cc_pll6_out_even_init = {
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.name = "cam_cc_pll6_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll6.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
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.offset = 0x6000,
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.post_div_shift = 10,
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@ -400,6 +568,20 @@ static const struct alpha_pll_config cam_cc_pll7_config = {
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_cam_cc_pll7_config = {
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.l = 0x2d,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll cam_cc_pll7 = {
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.offset = 0x7000,
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.vco_table = lucid_evo_vco,
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@ -420,6 +602,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
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{ }
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};
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static struct clk_init_data sm8475_cam_cc_pll7_out_even_init = {
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.name = "cam_cc_pll7_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll7.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
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.offset = 0x7000,
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.post_div_shift = 10,
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@ -448,6 +640,20 @@ static const struct alpha_pll_config cam_cc_pll8_config = {
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_cam_cc_pll8_config = {
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.l = 0x32,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll cam_cc_pll8 = {
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.offset = 0x8000,
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.vco_table = lucid_evo_vco,
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@ -468,6 +674,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
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{ }
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};
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static struct clk_init_data sm8475_cam_cc_pll8_out_even_init = {
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.name = "cam_cc_pll8_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll8.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
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.offset = 0x8000,
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.post_div_shift = 10,
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@ -2817,6 +3033,7 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = {
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static const struct of_device_id cam_cc_sm8450_match_table[] = {
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{ .compatible = "qcom,sm8450-camcc" },
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{ .compatible = "qcom,sm8475-camcc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
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@ -2829,15 +3046,72 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev)
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
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clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
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clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
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clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
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clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
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clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
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clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
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clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
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clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
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if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) {
|
||||
/* Update CAMCC PLL0 */
|
||||
cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll0_out_even.clkr.hw.init = &sm8475_cam_cc_pll0_out_even_init;
|
||||
cam_cc_pll0_out_odd.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll0_out_odd.clkr.hw.init = &sm8475_cam_cc_pll0_out_odd_init;
|
||||
|
||||
/* Update CAMCC PLL1 */
|
||||
cam_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll1_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll1_out_even.clkr.hw.init = &sm8475_cam_cc_pll1_out_even_init;
|
||||
|
||||
/* Update CAMCC PLL2 */
|
||||
cam_cc_pll2.vco_table = rivian_ole_vco;
|
||||
|
||||
/* Update CAMCC PLL3 */
|
||||
cam_cc_pll3.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll3_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll3_out_even.clkr.hw.init = &sm8475_cam_cc_pll3_out_even_init;
|
||||
|
||||
/* Update CAMCC PLL4 */
|
||||
cam_cc_pll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll4_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll4_out_even.clkr.hw.init = &sm8475_cam_cc_pll4_out_even_init;
|
||||
|
||||
/* Update CAMCC PLL5 */
|
||||
cam_cc_pll5.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll5_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll5_out_even.clkr.hw.init = &sm8475_cam_cc_pll5_out_even_init;
|
||||
|
||||
/* Update CAMCC PLL6 */
|
||||
cam_cc_pll6.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll6_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll6_out_even.clkr.hw.init = &sm8475_cam_cc_pll6_out_even_init;
|
||||
|
||||
/* Update CAMCC PLL7 */
|
||||
cam_cc_pll7.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll7_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll7_out_even.clkr.hw.init = &sm8475_cam_cc_pll7_out_even_init;
|
||||
|
||||
/* Update CAMCC PLL8 */
|
||||
cam_cc_pll8.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
|
||||
cam_cc_pll8_out_even.clkr.hw.init = &sm8475_cam_cc_pll8_out_even_init;
|
||||
|
||||
clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &sm8475_cam_cc_pll0_config);
|
||||
clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &sm8475_cam_cc_pll1_config);
|
||||
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &sm8475_cam_cc_pll2_config);
|
||||
clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &sm8475_cam_cc_pll3_config);
|
||||
clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &sm8475_cam_cc_pll4_config);
|
||||
clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &sm8475_cam_cc_pll5_config);
|
||||
clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &sm8475_cam_cc_pll6_config);
|
||||
clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &sm8475_cam_cc_pll7_config);
|
||||
clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &sm8475_cam_cc_pll8_config);
|
||||
} else {
|
||||
clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
|
||||
clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
|
||||
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
|
||||
clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
|
||||
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
|
||||
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
|
||||
clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
|
||||
clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
|
||||
clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
|
||||
}
|
||||
|
||||
return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap);
|
||||
}
|
||||
|
|
@ -2852,5 +3126,5 @@ static struct platform_driver cam_cc_sm8450_driver = {
|
|||
|
||||
module_platform_driver(cam_cc_sm8450_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver");
|
||||
MODULE_DESCRIPTION("QCOM CAMCC SM8450 / SM8475 Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user