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ASoC: amd: add vangogh i2s dai driver ops
Add Vangogh i2s dai driver ops. Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Link: https://lore.kernel.org/r/20210721180430.11571-10-Vijendar.Mukunda@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vijendar Mukunda
Mark Brown
parent
e550339ee6
commit
b80556addd
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@ -17,6 +17,344 @@
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#define DRV_NAME "acp5x_i2s_playcap"
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static int acp5x_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct i2s_dev_data *adata;
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int mode;
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adata = snd_soc_dai_get_drvdata(cpu_dai);
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mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
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switch (mode) {
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case SND_SOC_DAIFMT_I2S:
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adata->tdm_mode = TDM_DISABLE;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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adata->tdm_mode = TDM_ENABLE;
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break;
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default:
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return -EINVAL;
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}
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mode = fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
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switch (mode) {
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case SND_SOC_DAIFMT_CBC_CFC:
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adata->master_mode = I2S_MASTER_MODE_ENABLE;
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break;
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case SND_SOC_DAIFMT_CBP_CFP:
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adata->master_mode = I2S_MASTER_MODE_DISABLE;
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break;
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}
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return 0;
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}
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static int acp5x_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
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u32 tx_mask, u32 rx_mask,
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int slots, int slot_width)
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{
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struct i2s_dev_data *adata;
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u32 frm_len;
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u16 slot_len;
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adata = snd_soc_dai_get_drvdata(cpu_dai);
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/* These values are as per Hardware Spec */
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switch (slot_width) {
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case SLOT_WIDTH_8:
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slot_len = 8;
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break;
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case SLOT_WIDTH_16:
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slot_len = 16;
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break;
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case SLOT_WIDTH_24:
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slot_len = 24;
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break;
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case SLOT_WIDTH_32:
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slot_len = 0;
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break;
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default:
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return -EINVAL;
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}
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frm_len = FRM_LEN | (slots << 15) | (slot_len << 18);
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adata->tdm_fmt = frm_len;
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return 0;
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}
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static int acp5x_i2s_hwparams(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct i2s_stream_instance *rtd;
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struct snd_soc_pcm_runtime *prtd;
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struct snd_soc_card *card;
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struct acp5x_platform_info *pinfo;
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struct i2s_dev_data *adata;
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union acp_i2stdm_mstrclkgen mclkgen;
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u32 val;
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u32 reg_val, frmt_reg, master_reg;
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u32 lrclk_div_val, bclk_div_val;
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lrclk_div_val = 0;
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bclk_div_val = 0;
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prtd = asoc_substream_to_rtd(substream);
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rtd = substream->runtime->private_data;
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card = prtd->card;
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adata = snd_soc_dai_get_drvdata(dai);
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pinfo = snd_soc_card_get_drvdata(card);
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if (pinfo) {
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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rtd->i2s_instance = pinfo->play_i2s_instance;
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else
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rtd->i2s_instance = pinfo->cap_i2s_instance;
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}
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/* These values are as per Hardware Spec */
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_U8:
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case SNDRV_PCM_FORMAT_S8:
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rtd->xfer_resolution = 0x0;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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rtd->xfer_resolution = 0x02;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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rtd->xfer_resolution = 0x04;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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rtd->xfer_resolution = 0x05;
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break;
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default:
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_ITER;
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frmt_reg = ACP_HSTDM_TXFRMT;
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break;
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case I2S_SP_INSTANCE:
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default:
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reg_val = ACP_I2STDM_ITER;
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frmt_reg = ACP_I2STDM_TXFRMT;
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}
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} else {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_IRER;
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frmt_reg = ACP_HSTDM_RXFRMT;
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break;
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case I2S_SP_INSTANCE:
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default:
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reg_val = ACP_I2STDM_IRER;
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frmt_reg = ACP_I2STDM_RXFRMT;
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}
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}
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if (adata->tdm_mode) {
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val = acp_readl(rtd->acp5x_base + reg_val);
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acp_writel(val | 0x2, rtd->acp5x_base + reg_val);
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acp_writel(adata->tdm_fmt, rtd->acp5x_base + frmt_reg);
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}
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val = acp_readl(rtd->acp5x_base + reg_val);
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val &= ~ACP5x_ITER_IRER_SAMP_LEN_MASK;
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val = val | (rtd->xfer_resolution << 3);
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acp_writel(val, rtd->acp5x_base + reg_val);
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if (adata->master_mode) {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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master_reg = ACP_I2STDM2_MSTRCLKGEN;
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break;
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case I2S_SP_INSTANCE:
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default:
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master_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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}
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mclkgen.bits.i2stdm_master_mode = 0x1;
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if (adata->tdm_mode)
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mclkgen.bits.i2stdm_format_mode = 0x01;
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else
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mclkgen.bits.i2stdm_format_mode = 0x0;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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switch (params_rate(params)) {
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case 8000:
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bclk_div_val = 768;
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break;
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case 16000:
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bclk_div_val = 384;
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break;
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case 24000:
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bclk_div_val = 256;
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break;
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case 32000:
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bclk_div_val = 192;
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break;
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case 44100:
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case 48000:
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bclk_div_val = 128;
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break;
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case 88200:
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case 96000:
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bclk_div_val = 64;
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break;
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case 192000:
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bclk_div_val = 32;
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break;
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default:
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return -EINVAL;
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}
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lrclk_div_val = 32;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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switch (params_rate(params)) {
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case 8000:
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bclk_div_val = 384;
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break;
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case 16000:
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bclk_div_val = 192;
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break;
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case 24000:
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bclk_div_val = 128;
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break;
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case 32000:
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bclk_div_val = 96;
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break;
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case 44100:
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case 48000:
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bclk_div_val = 64;
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break;
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case 88200:
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case 96000:
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bclk_div_val = 32;
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break;
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case 192000:
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bclk_div_val = 16;
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break;
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default:
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return -EINVAL;
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}
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lrclk_div_val = 64;
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break;
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default:
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return -EINVAL;
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}
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mclkgen.bits.i2stdm_bclk_div_val = bclk_div_val;
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mclkgen.bits.i2stdm_lrclk_div_val = lrclk_div_val;
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acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
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}
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return 0;
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}
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static int acp5x_i2s_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct i2s_stream_instance *rtd;
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u32 ret, val, period_bytes, reg_val, ier_val, water_val;
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u32 buf_size, buf_reg;
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rtd = substream->runtime->private_data;
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period_bytes = frames_to_bytes(substream->runtime,
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substream->runtime->period_size);
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buf_size = frames_to_bytes(substream->runtime,
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substream->runtime->buffer_size);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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rtd->bytescount = acp_get_byte_count(rtd,
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substream->stream);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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water_val =
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ACP_HS_TX_INTR_WATERMARK_SIZE;
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reg_val = ACP_HSTDM_ITER;
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ier_val = ACP_HSTDM_IER;
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buf_reg = ACP_HS_TX_RINGBUFSIZE;
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break;
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case I2S_SP_INSTANCE:
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default:
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water_val =
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ACP_I2S_TX_INTR_WATERMARK_SIZE;
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reg_val = ACP_I2STDM_ITER;
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ier_val = ACP_I2STDM_IER;
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buf_reg = ACP_I2S_TX_RINGBUFSIZE;
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}
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} else {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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water_val =
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ACP_HS_RX_INTR_WATERMARK_SIZE;
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reg_val = ACP_HSTDM_IRER;
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ier_val = ACP_HSTDM_IER;
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buf_reg = ACP_HS_RX_RINGBUFSIZE;
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break;
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case I2S_SP_INSTANCE:
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default:
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water_val =
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ACP_I2S_RX_INTR_WATERMARK_SIZE;
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reg_val = ACP_I2STDM_IRER;
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ier_val = ACP_I2STDM_IER;
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buf_reg = ACP_I2S_RX_RINGBUFSIZE;
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}
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}
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acp_writel(period_bytes, rtd->acp5x_base + water_val);
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acp_writel(buf_size, rtd->acp5x_base + buf_reg);
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val = acp_readl(rtd->acp5x_base + reg_val);
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val = val | BIT(0);
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acp_writel(val, rtd->acp5x_base + reg_val);
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acp_writel(1, rtd->acp5x_base + ier_val);
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ret = 0;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_ITER;
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break;
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case I2S_SP_INSTANCE:
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default:
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reg_val = ACP_I2STDM_ITER;
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}
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} else {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_IRER;
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break;
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case I2S_SP_INSTANCE:
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default:
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reg_val = ACP_I2STDM_IRER;
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}
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}
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val = acp_readl(rtd->acp5x_base + reg_val);
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val = val & ~BIT(0);
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acp_writel(val, rtd->acp5x_base + reg_val);
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if (!(acp_readl(rtd->acp5x_base + ACP_HSTDM_ITER) & BIT(0)) &&
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!(acp_readl(rtd->acp5x_base + ACP_HSTDM_IRER) & BIT(0)))
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acp_writel(0, rtd->acp5x_base + ACP_HSTDM_IER);
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if (!(acp_readl(rtd->acp5x_base + ACP_I2STDM_ITER) & BIT(0)) &&
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!(acp_readl(rtd->acp5x_base + ACP_I2STDM_IRER) & BIT(0)))
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acp_writel(0, rtd->acp5x_base + ACP_I2STDM_IER);
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ret = 0;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static struct snd_soc_dai_ops acp5x_i2s_dai_ops = {
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.hw_params = acp5x_i2s_hwparams,
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.trigger = acp5x_i2s_trigger,
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.set_fmt = acp5x_i2s_set_fmt,
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.set_tdm_slot = acp5x_i2s_set_tdm_slot,
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};
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static const struct snd_soc_component_driver acp5x_dai_component = {
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.name = "acp5x-i2s",
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};
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@ -40,6 +378,7 @@ static struct snd_soc_dai_driver acp5x_i2s_dai = {
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.rate_min = 8000,
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.rate_max = 96000,
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},
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.ops = &acp5x_i2s_dai_ops,
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};
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static int acp5x_dai_probe(struct platform_device *pdev)
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@ -74,9 +74,20 @@
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#define I2S_MASTER_MODE_ENABLE 1
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#define I2S_MASTER_MODE_DISABLE 0
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#define SLOT_WIDTH_8 8
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#define SLOT_WIDTH_16 16
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#define SLOT_WIDTH_24 24
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#define SLOT_WIDTH_32 32
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#define TDM_ENABLE 1
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#define TDM_DISABLE 0
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#define ACP5x_ITER_IRER_SAMP_LEN_MASK 0x38
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struct i2s_dev_data {
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bool tdm_mode;
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bool master_mode;
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unsigned int i2s_irq;
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u16 i2s_instance;
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u32 tdm_fmt;
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void __iomem *acp5x_base;
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struct snd_pcm_substream *play_stream;
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struct snd_pcm_substream *capture_stream;
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@ -109,6 +120,17 @@ struct acp5x_platform_info {
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u16 cap_i2s_instance;
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};
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union acp_i2stdm_mstrclkgen {
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struct {
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u32 i2stdm_master_mode : 1;
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u32 i2stdm_format_mode : 1;
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u32 i2stdm_lrclk_div_val : 9;
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u32 i2stdm_bclk_div_val : 11;
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u32:10;
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} bitfields, bits;
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u32 u32_all;
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};
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/* common header file uses exact offset rather than relative
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* offset which requires subtraction logic from base_addr
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* for accessing ACP5x MMIO space registers
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