From b7ef8bbb9fbd43d33ecb92e23aa7c5a55dab5513 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Thu, 5 Mar 2026 16:16:37 +0300 Subject: [PATCH] media: ccs-pll: Fix pre-PLL divider calculation for EXT_IP_PLL_DIVIDER flag When the CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER flag is set, odd pre-PLL divider values are allowed. However, in the operational timing branch the calculation of the minimum pre-PLL divider incorrectly uses clk_div_even_up, forcing the minimum value to be even, even if the flag is set. This prevents selecting a valid odd divider like 3, which may be required for certain sensor configurations. Fix this by removing the forced even rounding from the minimum pre-PLL divider calculation. The loop later uses the flag to determine the step, so odd values will be considered when the flag is set. Signed-off-by: Alexander Shiyan Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/ccs-pll.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 4eb83636e102..1605cfa5db19 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -824,9 +824,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, op_lim_fr->min_pll_ip_clk_freq_hz)); min_op_pre_pll_clk_div = max_t(u16, op_lim_fr->min_pre_pll_clk_div, - clk_div_even_up( - DIV_ROUND_UP(pll->ext_clk_freq_hz, - op_lim_fr->max_pll_ip_clk_freq_hz))); + DIV_ROUND_UP(pll->ext_clk_freq_hz, + op_lim_fr->max_pll_ip_clk_freq_hz)); dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n", min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);