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ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt

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The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad
on the SoC.
Enable the interrupt function of the PHY's INTR32 pin to switch it from
it's default "receive error" mode to "interrupt pin" mode.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2019-01-19 00:43:37 +01:00 committed by Kevin Hilman
parent e7e871b50f
commit b7d10841e5
1 changed files with 4 additions and 0 deletions
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4
arch/arm/boot/dts/meson8b-ec100.dts
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@ -169,6 +169,10 @@ mdio {
eth_phy0: ethernet-phy@0 {
/* IC Plus IP101A/G (0x02430c54) */
reg = <0>;
icplus,select-interrupt;
interrupt-parent = <&gpio_intc>;
/* GPIOH_3 */
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
};
};