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drm/amdgpu: Add IH node-id to XCC mapping

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Add a generic function to map IH node-id to XCC instance.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mukul Joshi 2025-06-06 15:19:26 -04:00 committed by Alex Deucher
parent 4c5f7d7388
commit b79040d113
1 changed files with 29 additions and 4 deletions
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33
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
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@ -698,6 +698,18 @@ static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev)
return 1;
}
static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
{
int xcc = (ih_node & 0x7) - 2 + (ih_node >> 3) * 4;
if (xcc < 0 || xcc >= hweight8(adev->gfx.xcc_mask)) {
dev_err(adev->dev, "Couldn't find xcc mapping from IH node");
return -EINVAL;
}
return xcc;
}
static const struct amdgpu_gfx_funcs gfx_v12_1_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v12_1_get_gpu_clock_counter,
.select_se_sh = &gfx_v12_1_xcc_select_se_sh,
@ -707,6 +719,7 @@ static const struct amdgpu_gfx_funcs gfx_v12_1_gfx_funcs = {
.select_me_pipe_q = &gfx_v12_1_select_me_pipe_q,
.update_perfmon_mgcg = &gfx_v12_1_update_perf_clk,
.get_xccs_per_xcp = &gfx_v12_1_get_xccs_per_xcp,
.ih_node_to_logical_xcc = &gfx_v12_1_ih_to_xcc_inst,
};
static int gfx_v12_1_gpu_early_init(struct amdgpu_device *adev)
@ -3414,7 +3427,7 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
int i;
int i, xcc_id;
u8 me_id, pipe_id, queue_id;
struct amdgpu_ring *ring;
uint32_t mes_queue_id = entry->src_data[0];
@ -3437,6 +3450,10 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev,
me_id = (entry->ring_id & 0x0c) >> 2;
pipe_id = (entry->ring_id & 0x03) >> 0;
queue_id = (entry->ring_id & 0x70) >> 4;
xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id);
if (xcc_id == -EINVAL)
return -EINVAL;
switch (me_id) {
case 0:
@ -3448,7 +3465,9 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev,
case 1:
case 2:
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
ring = &adev->gfx.compute_ring
[i +
xcc_id * adev->gfx.num_compute_rings];
/* Per-queue interrupt is supported for MEC starting from VI.
* The interrupt can only be enabled/disabled per pipe instead
* of per queue.
@ -3516,11 +3535,15 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev,
{
u8 me_id, pipe_id, queue_id;
struct amdgpu_ring *ring;
int i;
int i, xcc_id;
me_id = (entry->ring_id & 0x0c) >> 2;
pipe_id = (entry->ring_id & 0x03) >> 0;
queue_id = (entry->ring_id & 0x70) >> 4;
xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id);
if (xcc_id == -EINVAL)
return;
switch (me_id) {
case 0:
@ -3534,7 +3557,9 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev,
case 1:
case 2:
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
ring = &adev->gfx.compute_ring
[i +
xcc_id * adev->gfx.num_compute_rings];
if (ring->me == me_id && ring->pipe == pipe_id &&
ring->queue == queue_id)
drm_sched_fault(&ring->sched);