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net: phy: realtek: add support for RTL8261C_CG
This patch adds support for Realtek phy chip RTL8261C_CG. Its PHY ID is 0x001cc898. This patch introduces a distinct family of handlers (probe, get_features, config_aneg, read_status, config_intr, handle_interrupt). Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Nicolai Buchwitz <nb@tipi-net.de> Signed-off-by: Javen Xu <javen_xu@realsil.com.cn> Link: https://patch.msgid.link/20260728073106.1515-4-javen_xu@realsil.com.cn Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Javen Xu
Jakub Kicinski
parent
d7722c0308
commit
b772b5ae45
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@ -141,6 +141,10 @@
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#define RTL8211F_PHYSICAL_ADDR_WORD1 17
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#define RTL8211F_PHYSICAL_ADDR_WORD2 18
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#define RTL8261X_EXT_ADDR_REG 0xa436
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#define RTL8261X_EXT_DATA_REG 0xa438
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#define RTL_8261X_SUB_PHY_ID_ADDR 0x801d
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#define RTL822X_VND1_SERDES_OPTION 0x697a
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#define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
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#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
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@ -251,6 +255,32 @@
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#define RTL_8221B_VM_CG 0x001cc84a
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#define RTL_8251B 0x001cc862
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#define RTL_8261C 0x001cc890
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#define RTL_8261C_CG 0x001cc898
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#define RTL8261C_CE_MODEL 0x00
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#define RTL8261X_INT_AUTONEG_ERROR BIT(0)
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#define RTL8261X_INT_PAGE_RECV BIT(2)
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#define RTL8261X_INT_AUTONEG_DONE BIT(3)
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#define RTL8261X_INT_LINK_CHG BIT(4)
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#define RTL8261X_INT_PHY_REG_ACCESS BIT(5)
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#define RTL8261X_INT_PME BIT(7)
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#define RTL8261X_INT_ALDPS_CHG BIT(9)
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#define RTL8261X_INT_JABBER BIT(10)
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#define RTL8261X_INT_MASK_DEFAULT (RTL8261X_INT_AUTONEG_DONE | \
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RTL8261X_INT_LINK_CHG | \
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RTL8261X_INT_AUTONEG_ERROR | \
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RTL8261X_INT_JABBER)
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#define RTL8261X_INT_MASK_ALL (RTL8261X_INT_AUTONEG_ERROR | \
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RTL8261X_INT_PAGE_RECV | \
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RTL8261X_INT_AUTONEG_DONE | \
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RTL8261X_INT_LINK_CHG | \
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RTL8261X_INT_PHY_REG_ACCESS | \
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RTL8261X_INT_PME | \
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RTL8261X_INT_ALDPS_CHG | \
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RTL8261X_INT_JABBER)
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/* RTL8211E and RTL8211F support up to three LEDs */
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#define RTL8211x_LED_COUNT 3
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@ -310,6 +340,156 @@ static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page,
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return phy_restore_page(phydev, oldpage, ret);
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}
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static int rtl8261x_probe(struct phy_device *phydev)
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{
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int sub_phy_id, ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8261X_EXT_ADDR_REG,
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RTL_8261X_SUB_PHY_ID_ADDR);
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if (ret < 0)
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return ret;
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8261X_EXT_DATA_REG);
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if (ret < 0)
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return ret;
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sub_phy_id = (ret >> 8) & 0xff;
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switch (sub_phy_id) {
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case RTL8261C_CE_MODEL:
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phydev_info(phydev, "RTL8261C detected (sub_id 0x%02x)\n", sub_phy_id);
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break;
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default:
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phydev_warn(phydev, "Unknown sub_id 0x%02x, default behavior\n", sub_phy_id);
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return -ENODEV;
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}
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return 0;
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}
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static int rtl8261x_get_features(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_c45_pma_read_abilities(phydev);
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if (ret)
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return ret;
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/*
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* Supplement Multi-Gig speeds that may not be automatically detected
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* RTL8261X supports 2.5G/5G in addition to standard 10G
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*/
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linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
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phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
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phydev->supported);
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return 0;
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}
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static int rtl8261x_read_status(struct phy_device *phydev)
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{
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int ret, val = 0;
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if (phydev->autoneg == AUTONEG_ENABLE) {
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ret = genphy_c45_aneg_done(phydev);
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if (ret < 0)
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return ret;
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if (ret) {
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val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
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RTL822X_VND2_C22_REG(MII_STAT1000));
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if (val < 0)
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return val;
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}
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}
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mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
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ret = genphy_c45_read_status(phydev);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int rtl8261x_config_intr(struct phy_device *phydev)
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{
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int ret;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR);
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if (ret < 0)
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return ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER,
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RTL8261X_INT_MASK_DEFAULT);
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if (ret < 0)
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return ret;
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} else {
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 0);
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if (ret < 0)
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return ret;
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static irqreturn_t rtl8261x_handle_interrupt(struct phy_device *phydev)
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{
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int irq_status;
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irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR);
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if (irq_status < 0) {
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phy_error(phydev);
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return IRQ_NONE;
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}
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if (!(irq_status & RTL8261X_INT_MASK_ALL))
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return IRQ_NONE;
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if (irq_status & (RTL8261X_INT_LINK_CHG | RTL8261X_INT_AUTONEG_DONE |
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RTL8261X_INT_AUTONEG_ERROR | RTL8261X_INT_JABBER))
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phy_trigger_machine(phydev);
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return IRQ_HANDLED;
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}
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static int rtl8261x_config_aneg(struct phy_device *phydev)
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{
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u16 adv_1g = 0;
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int ret;
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ret = genphy_c45_config_aneg(phydev);
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if (ret < 0)
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return ret;
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if (phydev->autoneg == AUTONEG_DISABLE)
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return 0;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->advertising))
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adv_1g = ADVERTISE_1000FULL;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
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phydev->advertising))
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adv_1g |= ADVERTISE_1000HALF;
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2,
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RTL822X_VND2_C22_REG(MII_CTRL1000),
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ADVERTISE_1000FULL | ADVERTISE_1000HALF,
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adv_1g);
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if (ret < 0)
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return ret;
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if (ret > 0)
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return genphy_c45_restart_aneg(phydev);
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return 0;
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}
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static int rtl821x_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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@ -3002,6 +3182,18 @@ static struct phy_driver realtek_drvs[] = {
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.resume = genphy_resume,
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.read_mmd = genphy_read_mmd_unsupported,
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.write_mmd = genphy_write_mmd_unsupported,
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}, {
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PHY_ID_MATCH_EXACT(RTL_8261C_CG),
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.name = "Realtek RTL8261C 10Gbps PHY",
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.probe = rtl8261x_probe,
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.get_features = rtl8261x_get_features,
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.config_aneg = rtl8261x_config_aneg,
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.read_status = rtl8261x_read_status,
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.config_intr = rtl8261x_config_intr,
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.handle_interrupt = rtl8261x_handle_interrupt,
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.soft_reset = genphy_c45_pma_soft_reset,
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.suspend = genphy_c45_pma_suspend,
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.resume = genphy_c45_pma_resume,
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},
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};
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