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arm64: dts: socfpga: agilex5: add NAND daughter board
The Agilex5 devkit supports a separate NAND daughter card. The NAND daughter card replaces the SDMMC slot that is on the default daughter card thus requires a separate board dts file. Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
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socfpga_agilex_socdk.dtb \
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socfpga_agilex_socdk_nand.dtb \
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socfpga_agilex5_socdk.dtb \
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socfpga_agilex5_socdk_nand.dtb \
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socfpga_n5x_socdk.dtb
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dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
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89
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
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89
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
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@ -0,0 +1,89 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025, Altera Corporation
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*/
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#include "socfpga_agilex5.dtsi"
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/ {
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model = "SoCFPGA Agilex5 SoCDK NAND daughter board";
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compatible = "intel,socfpga-agilex5-socdk-nand", "intel,socfpga-agilex5";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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led0 {
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label = "hps_led0";
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gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
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};
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led1 {
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label = "hps_led1";
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gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i3c0 {
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status = "okay";
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};
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&i3c1 {
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status = "okay";
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};
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&nand {
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status = "okay";
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nand@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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nand-bus-width = <8>;
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partition@0 {
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label = "u-boot";
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reg = <0 0x200000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x200000 0xffe00000>;
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};
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};
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};
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&osc1 {
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clock-frequency = <25000000>;
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};
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&uart0 {
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status = "okay";
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};
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&watchdog0 {
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status = "okay";
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};
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