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pinctrl: renesas: r8a77970: Add bias pinconf support
Implement support for pull-up (most pins, excl. DU_DOTCLKIN and EXTALR) and pull-down (most pins, excl. JTAG) handling for the R-Car V3M SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/bcfad447624d874258a45a92554574b8fe9f712f.1619785375.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
parent
009f502238
commit
b764833e36
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@ -19,12 +19,23 @@
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#include "sh_pfc.h"
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_28(1, fn, sfx), \
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PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_6(4, fn, sfx), \
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PORT_GP_15(5, fn, sfx)
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PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
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#define CPU_ALL_NOGP(fn) \
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PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
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PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
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PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
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/*
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* F_() : just information
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* FM() : macro for FN_xxx / xxx_MARK
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@ -718,8 +729,17 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
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};
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/*
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* Pins not associated with a GPIO port.
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*/
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enum {
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GP_ASSIGN_LAST(),
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NOGP_ALL(),
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};
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static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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PINMUX_NOGP_ALL(),
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};
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/* - AVB0 ------------------------------------------------------------------- */
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@ -2496,8 +2516,150 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
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return -EINVAL;
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}
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static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
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[ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
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[ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
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[ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
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[ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
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[ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
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[ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
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[ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
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[ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
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[ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
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[ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
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[10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
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[11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
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[12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
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[13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
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[14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
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[15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
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[16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
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[17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
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[18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
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[19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
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[20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
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[21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
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[22] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
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[23] = PIN_PRESETOUT_N, /* PRESETOUT# */
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[24] = PIN_EXTALR, /* EXTALR */
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[25] = PIN_FSCLKST_N, /* FSCLKST# */
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[26] = RCAR_GP_PIN(1, 0), /* IRQ0 */
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[27] = PIN_TRST_N, /* TRST# */
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[28] = PIN_TCK, /* TCK */
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[29] = PIN_TMS, /* TMS */
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[30] = PIN_TDI, /* TDI */
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[31] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
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} },
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{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
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[ 0] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
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[ 1] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
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[ 2] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
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[ 3] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
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[ 4] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
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[ 5] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
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[ 6] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
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[ 7] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
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[ 8] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
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[ 9] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
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[10] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
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[11] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
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[12] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
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[13] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
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[14] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
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[15] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
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[16] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
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[17] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
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[18] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
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[19] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
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[20] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
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[21] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
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[22] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
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[23] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
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[24] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
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[25] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
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[26] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
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[27] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
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[28] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
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[29] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
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[30] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
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[31] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
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} },
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{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
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[ 0] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
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[ 1] = RCAR_GP_PIN(4, 0), /* SCL0 */
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[ 2] = RCAR_GP_PIN(4, 1), /* SDA0 */
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[ 3] = RCAR_GP_PIN(4, 2), /* SCL1 */
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[ 4] = RCAR_GP_PIN(4, 3), /* SDA1 */
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[ 5] = RCAR_GP_PIN(4, 4), /* SCL2 */
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[ 6] = RCAR_GP_PIN(4, 5), /* SDA2 */
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[ 7] = RCAR_GP_PIN(1, 1), /* AVB0_RX_CTL */
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[ 8] = RCAR_GP_PIN(1, 2), /* AVB0_RXC */
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[ 9] = RCAR_GP_PIN(1, 3), /* AVB0_RD0 */
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[10] = RCAR_GP_PIN(1, 4), /* AVB0_RD1 */
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[11] = RCAR_GP_PIN(1, 5), /* AVB0_RD2 */
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[12] = RCAR_GP_PIN(1, 6), /* AVB0_RD3 */
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[13] = RCAR_GP_PIN(1, 7), /* AVB0_TX_CTL */
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[14] = RCAR_GP_PIN(1, 8), /* AVB0_TXC */
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[15] = RCAR_GP_PIN(1, 9), /* AVB0_TD0 */
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[16] = RCAR_GP_PIN(1, 10), /* AVB0_TD1 */
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[17] = RCAR_GP_PIN(1, 11), /* AVB0_TD2 */
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[18] = RCAR_GP_PIN(1, 12), /* AVB0_TD3 */
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[19] = RCAR_GP_PIN(1, 13), /* AVB0_TXCREFCLK */
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[20] = RCAR_GP_PIN(1, 14), /* AVB0_MDIO */
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[21] = RCAR_GP_PIN(1, 15), /* AVB0_MDC */
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[22] = RCAR_GP_PIN(1, 16), /* AVB0_MAGIC */
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[23] = RCAR_GP_PIN(1, 17), /* AVB0_PHY_INT */
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[24] = RCAR_GP_PIN(1, 18), /* AVB0_LINK */
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[25] = RCAR_GP_PIN(1, 19), /* AVB0_AVTP_MATCH */
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[26] = RCAR_GP_PIN(1, 20), /* AVB0_AVTP_CAPTURE */
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[27] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
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[28] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
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[29] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
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[30] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
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[31] = RCAR_GP_PIN(1, 25), /* CANFD_CLK */
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} },
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{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
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[ 0] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
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[ 1] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
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[ 2] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
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[ 3] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
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[ 4] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
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[ 5] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
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[ 6] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
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[ 7] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
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[ 8] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
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[ 9] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
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[10] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
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[11] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
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[12] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
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[13] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
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[14] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
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[15] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
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[16] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
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[17] = SH_PFC_PIN_NONE,
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[18] = SH_PFC_PIN_NONE,
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[19] = SH_PFC_PIN_NONE,
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[20] = SH_PFC_PIN_NONE,
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[21] = SH_PFC_PIN_NONE,
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[22] = SH_PFC_PIN_NONE,
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[23] = SH_PFC_PIN_NONE,
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[24] = SH_PFC_PIN_NONE,
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[25] = SH_PFC_PIN_NONE,
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[26] = SH_PFC_PIN_NONE,
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[27] = SH_PFC_PIN_NONE,
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[28] = SH_PFC_PIN_NONE,
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[29] = SH_PFC_PIN_NONE,
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[30] = SH_PFC_PIN_NONE,
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[31] = SH_PFC_PIN_NONE,
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} },
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{ /* sentinel */ }
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};
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static const struct sh_pfc_soc_operations pinmux_ops = {
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.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
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.get_bias = rcar_pinmux_get_bias,
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.set_bias = rcar_pinmux_set_bias,
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};
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const struct sh_pfc_soc_info r8a77970_pinmux_info = {
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@ -2515,6 +2677,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = {
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.nr_functions = ARRAY_SIZE(pinmux_functions),
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.cfg_regs = pinmux_config_regs,
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.bias_regs = pinmux_bias_regs,
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.ioctrl_regs = pinmux_ioctrl_regs,
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.pinmux_data = pinmux_data,
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