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arm64: dts: qcom: x1e80100: describe USB signals properly

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Follow example of other platforms. Rename HS graph nodes to contain
'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-8-ad153c747a97@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2024-05-12 01:04:14 +03:00 committed by Bjorn Andersson
parent 93830ef7bb
commit b73ed308f9
1 changed files with 141 additions and 8 deletions
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149
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@ -2543,6 +2543,33 @@ usb_1_ss0_qmpphy: phy@fd5000 {
#phy-cells = <1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_ss0_qmpphy_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_ss0_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_1_ss0_dwc3_ss>;
};
};
port@2 {
reg = <2>;
usb_1_ss0_qmpphy_dp_in: endpoint {
};
};
};
};
usb_1_ss1_hsphy: phy@fd9000 {
@ -2583,6 +2610,33 @@ usb_1_ss1_qmpphy: phy@fda000 {
#phy-cells = <1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_ss1_qmpphy_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_ss1_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_1_ss1_dwc3_ss>;
};
};
port@2 {
reg = <2>;
usb_1_ss1_qmpphy_dp_in: endpoint {
};
};
};
};
usb_1_ss2_hsphy: phy@fde000 {
@ -2623,6 +2677,33 @@ usb_1_ss2_qmpphy: phy@fdf000 {
#phy-cells = <1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_ss2_qmpphy_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_ss2_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_1_ss2_dwc3_ss>;
};
};
port@2 {
reg = <2>;
usb_1_ss2_qmpphy_dp_in: endpoint {
};
};
};
};
cnoc_main: interconnect@1500000 {
@ -3445,8 +3526,23 @@ usb_1_ss2_dwc3: usb@a000000 {
dma-coherent;
port {
usb_1_ss2_role_switch: endpoint {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_ss2_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_ss2_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
};
};
};
};
@ -3514,8 +3610,15 @@ usb_2_dwc3: usb@a200000 {
phy-names = "usb2-phy";
maximum-speed = "high-speed";
port {
usb_2_role_switch: endpoint {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_2_dwc3_hs: endpoint {
};
};
};
};
@ -3590,8 +3693,23 @@ usb_1_ss0_dwc3: usb@a600000 {
dma-coherent;
port {
usb_1_ss0_role_switch: endpoint {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_ss0_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_ss0_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
};
};
};
};
@ -3673,8 +3791,23 @@ usb_1_ss1_dwc3: usb@a800000 {
dma-coherent;
port {
usb_1_ss1_role_switch: endpoint {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_ss1_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_ss1_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
};
};
};
};