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arm64: dts: renesas: r9a08g045: Add OPP table

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Add OPP table for the Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250128145616.2691841-1-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea 2025-01-28 16:56:16 +02:00 committed by Geert Uytterhoeven
parent 0c507d15f0
commit b6f4b126b2
1 changed files with 28 additions and 0 deletions
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28
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
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@ -28,6 +28,33 @@ audio_clk2: audio2-clk {
clock-frequency = <0>;
};
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-137500000 {
opp-hz = /bits/ 64 <137500000>;
opp-microvolt = <940000>;
clock-latency-ns = <300000>;
};
opp-275000000 {
opp-hz = /bits/ 64 <275000000>;
opp-microvolt = <940000>;
clock-latency-ns = <300000>;
};
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
opp-microvolt = <940000>;
clock-latency-ns = <300000>;
};
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <940000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -40,6 +67,7 @@ cpu0: cpu@0 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {