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drm/amd/display: DML21 Fixes

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- Store state related info inside mode_lib.
- Fix bad DCFCLK deep sleep
- Update FAMS structure in DMUB header

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Austin Zheng 2025-04-14 16:49:13 -04:00 committed by Alex Deucher
parent 6123117005
commit b6943f4adc
7 changed files with 116 additions and 15 deletions
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1
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top.h
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@ -43,5 +43,4 @@ bool dml2_build_mode_programming(struct dml2_build_mode_programming_in_out *in_o
*/
bool dml2_build_mcache_programming(struct dml2_build_mcache_programming_in_out *in_out);
#endif

10
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
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@ -279,7 +279,10 @@ struct dml2_per_stream_programming {
} phantom_stream;
union dmub_cmd_fams2_config fams2_base_params;
union dmub_cmd_fams2_config fams2_sub_params;
union {
union dmub_cmd_fams2_config fams2_sub_params;
union dmub_fams2_stream_static_sub_state_v2 fams2_sub_params_v2;
};
};
//-----------------
@ -674,9 +677,14 @@ struct dml2_display_cfg_programming {
// unlimited # of mcache
struct dml2_mcache_surface_allocation non_optimized_mcache_allocation[DML2_MAX_PLANES];
bool failed_prefetch;
bool failed_uclk_pstate;
bool failed_mcache_validation;
bool failed_dpmm;
bool failed_mode_programming;
bool failed_mode_programming_dcfclk;
bool failed_mode_programming_prefetch;
bool failed_mode_programming_flip;
bool failed_map_watermarks;
} informative;
};

7
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
View File

@ -7905,6 +7905,7 @@ static noinline_for_stack void dml_core_ms_prefetch_check(struct dml2_core_inter
}
static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out_params)
{
struct dml2_core_internal_display_mode_lib *mode_lib = in_out_params->mode_lib;
@ -11880,7 +11881,7 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex
}
//Maximum Bandwidth Used
s->TotalWRBandwidth = 0;
mode_lib->mp.TotalWRBandwidth = 0;
for (k = 0; k < display_cfg->num_streams; ++k) {
s->WRBandwidth = 0;
if (display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream > 0) {
@ -11889,7 +11890,7 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex
(display_cfg->stream_descriptors[k].timing.h_total * display_cfg->stream_descriptors[k].writeback.writeback_stream[0].input_height
/ ((double)display_cfg->stream_descriptors[k].timing.pixel_clock_khz / 1000))
* (display_cfg->stream_descriptors[k].writeback.writeback_stream[0].pixel_format == dml2_444_32 ? 4.0 : 8.0);
s->TotalWRBandwidth = s->TotalWRBandwidth + s->WRBandwidth;
mode_lib->mp.TotalWRBandwidth = mode_lib->mp.TotalWRBandwidth + s->WRBandwidth;
}
}
@ -13243,7 +13244,7 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod
out->informative.misc.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeLumaPrefetch[k];
out->informative.misc.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeChromaPrefetch[k];
out->informative.misc.WritebackRequiredBandwidth = mode_lib->scratch.dml_core_mode_programming_locals.TotalWRBandwidth / 1000.0;
out->informative.misc.WritebackRequiredBandwidth = mode_lib->mp.TotalWRBandwidth / 1000.0;
out->informative.misc.WritebackAllowDRAMClockChangeEndPosition[k] = mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k];
out->informative.misc.WritebackAllowFCLKChangeEndPosition[k] = mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k];
out->informative.misc.DSCCLK_calculated[k] = mode_lib->mp.DSCCLK[k];

82
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
View File

@ -329,6 +329,7 @@ struct dml2_core_internal_mode_support_info {
bool temp_read_or_ppt_support;
struct dml2_core_internal_watermarks watermarks;
bool dcfclk_support;
};
struct dml2_core_internal_mode_support {
@ -350,9 +351,11 @@ struct dml2_core_internal_mode_support {
double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
double GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes
double GlobalDTBCLK; /// <brief the Max DTBCLK freq out of all pipes
double uclk_freq_mhz;
double dram_bw_mbps;
double max_dram_bw_mbps;
double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps
double MaxFabricClock; /// <brief Basically just the clock freq at the min (or given) state
double MaxDCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
@ -473,9 +476,19 @@ struct dml2_core_internal_mode_support {
bool RequiresDSC[DML2_MAX_PLANES];
bool RequiresFEC[DML2_MAX_PLANES];
double OutputBpp[DML2_MAX_PLANES];
double DesiredOutputBpp[DML2_MAX_PLANES];
double PixelClockBackEnd[DML2_MAX_PLANES];
unsigned int DSCDelay[DML2_MAX_PLANES];
enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];
enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES];
bool TotalAvailablePipesSupportNoDSC;
bool TotalAvailablePipesSupportDSC;
unsigned int NumberOfDPPNoDSC;
unsigned int NumberOfDPPDSC;
enum dml2_odm_mode ODMModeNoDSC;
enum dml2_odm_mode ODMModeDSC;
double RequiredDISPCLKPerSurfaceNoDSC;
double RequiredDISPCLKPerSurfaceDSC;
// Bandwidth Related Info
double BandwidthAvailableForImmediateFlip;
@ -538,7 +551,41 @@ struct dml2_core_internal_mode_support {
bool mall_comb_mcache_c[DML2_MAX_PLANES];
bool lc_comb_mcache[DML2_MAX_PLANES];
unsigned int vmpg_width_y[DML2_MAX_PLANES];
unsigned int vmpg_height_y[DML2_MAX_PLANES];
unsigned int vmpg_width_c[DML2_MAX_PLANES];
unsigned int vmpg_height_c[DML2_MAX_PLANES];
unsigned int meta_row_height_luma[DML2_MAX_PLANES];
unsigned int meta_row_height_chroma[DML2_MAX_PLANES];
unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];
unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];
unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];
unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];
unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];
unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];
unsigned int MaximumVStartup[DML2_MAX_PLANES];
double HostVMInefficiencyFactor;
double HostVMInefficiencyFactorPrefetch;
unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];
unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];
double tdlut_opt_time[DML2_MAX_PLANES];
double tdlut_drain_time[DML2_MAX_PLANES];
unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];
double Tvm_trips_flip[DML2_MAX_PLANES];
double Tr0_trips_flip[DML2_MAX_PLANES];
double Tvm_trips_flip_rounded[DML2_MAX_PLANES];
double Tr0_trips_flip_rounded[DML2_MAX_PLANES];
unsigned int DSTYAfterScaler[DML2_MAX_PLANES];
unsigned int DSTXAfterScaler[DML2_MAX_PLANES];
};
/// @brief A mega structure that houses various info for model programming step.
@ -548,6 +595,7 @@ struct dml2_core_internal_mode_program {
double FabricClock; /// <brief Basically just the clock freq at the min (or given) state
//double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
double dram_bw_mbps;
double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps
double uclk_freq_mhz;
unsigned int NoOfDPP[DML2_MAX_PLANES];
enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];
@ -684,6 +732,38 @@ struct dml2_core_internal_mode_program {
double TCalc;
unsigned int TotImmediateFlipBytes;
unsigned int MaxTotalDETInKByte;
unsigned int NomDETInKByte;
unsigned int MinCompressedBufferSizeInKByte;
double PixelClockBackEnd[DML2_MAX_PLANES];
double OutputBpp[DML2_MAX_PLANES];
bool dsc_enable[DML2_MAX_PLANES];
unsigned int num_dsc_slices[DML2_MAX_PLANES];
unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];
unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];
unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];
unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];
unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG
double HostVMInefficiencyFactor;
double HostVMInefficiencyFactorPrefetch;
unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];
unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];
unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];
double tdlut_opt_time[DML2_MAX_PLANES];
double tdlut_drain_time[DML2_MAX_PLANES];
unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];
double Tvm_trips_flip[DML2_MAX_PLANES];
double Tr0_trips_flip[DML2_MAX_PLANES];
double Tvm_trips_flip_rounded[DML2_MAX_PLANES];
double Tr0_trips_flip_rounded[DML2_MAX_PLANES];
bool immediate_flip_required; // any pipes need immediate flip
double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
double TotalWRBandwidth;
double max_urgent_latency_us;
double df_response_time_us;
// -------------------
// Output
// -------------------
@ -697,6 +777,7 @@ struct dml2_core_internal_mode_program {
bool PrefetchModeSupported; // <brief Is the prefetch mode (bandwidth and latency) supported
bool ImmediateFlipSupported;
bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];
bool dcfclk_support;
// Clock
double Dcfclk;
@ -1028,7 +1109,6 @@ struct dml2_core_calcs_mode_programming_locals {
double dlg_vblank_start;
double LSetup;
double blank_lines_remaining;
double TotalWRBandwidth;
double WRBandwidth;
struct dml2_core_internal_DmlPipe myPipe;
double PixelClockBackEndFactor;

3
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
View File

@ -389,9 +389,6 @@ static bool map_min_clocks_to_dpm(const struct dml2_core_mode_support_result *mo
if (result)
result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.dispclk_khz, &state_table->dispclk);
if (result)
result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.deepsleep_dcfclk_khz, &state_table->dcfclk);
for (i = 0; i < DML2_MAX_DCN_PIPES; i++) {
if (result)
result = round_up_to_next_dpm(&display_cfg->plane_programming[i].min_clocks.dcn4x.dppclk_khz, &state_table->dppclk);

10
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
View File

@ -202,6 +202,8 @@ struct dml2_core_mode_support_result {
} active;
unsigned int dispclk_khz;
unsigned int dpprefclk_khz;
unsigned int dtbrefclk_khz;
unsigned int dcfclk_deepsleep_khz;
unsigned int socclk_khz;
@ -446,13 +448,17 @@ struct dml2_core_internal_state_intermediates {
};
struct dml2_core_mode_support_locals {
struct dml2_core_calcs_mode_support_ex mode_support_ex_params;
union {
struct dml2_core_calcs_mode_support_ex mode_support_ex_params;
};
struct dml2_display_cfg svp_expanded_display_cfg;
struct dml2_calculate_mcache_allocation_in_out calc_mcache_allocation_params;
};
struct dml2_core_mode_programming_locals {
struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params;
union {
struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params;
};
struct dml2_display_cfg svp_expanded_display_cfg;
};

18
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
View File

@ -104,6 +104,14 @@
*/
#define DMUB_MAX_FPO_STREAMS 4
/* Define to ensure that the "common" members always appear in the same
* order in different structs for back compat purposes
*/
#define COMMON_STREAM_STATIC_SUB_STATE \
struct dmub_fams2_cmd_legacy_stream_static_state legacy; \
struct dmub_fams2_cmd_subvp_stream_static_state subvp; \
struct dmub_fams2_cmd_drr_stream_static_state drr;
/* Maximum number of streams on any ASIC. */
#define DMUB_MAX_STREAMS 6
@ -2021,11 +2029,13 @@ union dmub_fams2_stream_static_sub_state {
}; //v0
union dmub_fams2_cmd_stream_static_sub_state {
struct dmub_fams2_cmd_legacy_stream_static_state legacy;
struct dmub_fams2_cmd_subvp_stream_static_state subvp;
struct dmub_fams2_cmd_drr_stream_static_state drr;
COMMON_STREAM_STATIC_SUB_STATE
}; //v1
union dmub_fams2_stream_static_sub_state_v2 {
COMMON_STREAM_STATIC_SUB_STATE
}; //v2
struct dmub_fams2_stream_static_state {
enum fams2_stream_type type;
uint32_t otg_vline_time_ns;
@ -2091,7 +2101,7 @@ struct dmub_fams2_cmd_stream_static_base_state {
struct dmub_fams2_stream_static_state_v1 {
struct dmub_fams2_cmd_stream_static_base_state base;
union dmub_fams2_cmd_stream_static_sub_state sub_state;
union dmub_fams2_stream_static_sub_state_v2 sub_state;
}; //v1
/**