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arm64: dts: qcom: lemans-evk: Add IFP Mezzanine
The Interface Plus [IFP] Mezzanine is an hardware expansion add-on
board designed to be stacked on top of Lemans EVK.
It has following peripherals :
- 4x Type A USB ports in host mode.
- TC9563 PCIe switch, which has following three downstream ports (DSP) :
- 1st DSP is routed to an M.2 E-key connector, intended for
WLAN modules.
- 2nd DSP is routed to an M.2 B-key connector, intended for
cellular modems.
- 3rd DSP with support for Dual Ethernet ports.
- eMMC.
- Additional 2.5GbE Ethernet PHY connected to native EMAC with support for
MAC Address configuration via NVMEM.
- EEPROM.
- LVDS Display.
- 2*mini DP.
Add support for following peripherals :
- TC9563 PCIe Switch.
- Additional 2.5GbE Ethernet Port.
- EEPROM.
Enable support for USB hub, LVDS display and mini-DP later once
dependent changes are available in lemans-evk core-kit.
Written with inputs from :
Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> - Ethernet.
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> - PCIe
Monish Chunara <monish.chunara@oss.qualcomm.com> - EEPROM.
Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304165925.1535938-2-umang.chheda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Umang Chheda
Bjorn Andersson
parent
5a67924d2f
commit
b64abb26a2
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@ -50,6 +50,8 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb
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lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb
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lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb
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dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb
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dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb
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263
arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
Normal file
263
arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
Normal file
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@ -0,0 +1,263 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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&{/} {
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model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine";
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vreg_0p9: regulator-0v9 {
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compatible = "regulator-fixed";
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regulator-name = "VREG_0P9";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vreg_1p8: regulator-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "VREG_1P8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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ðernet1 {
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phy-handle = <&hsgmii_phy1>;
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phy-mode = "2500base-x";
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pinctrl-0 = <ðernet1_default>;
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pinctrl-names = "default";
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snps,mtl-rx-config = <&mtl_rx_setup1>;
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snps,mtl-tx-config = <&mtl_tx_setup1>;
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nvmem-cells = <&mac_addr1>;
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nvmem-cell-names = "mac-address";
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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hsgmii_phy1: ethernet-phy@18 {
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compatible = "ethernet-phy-id004d.d101";
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reg = <0x18>;
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reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
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reset-assert-us = <11000>;
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reset-deassert-us = <70000>;
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};
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};
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mtl_rx_setup1: rx-queues-config {
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snps,rx-queues-to-use = <4>;
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snps,rx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <0x0>;
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snps,route-up;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <0x1>;
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snps,route-ptp;
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};
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queue2 {
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snps,avb-algorithm;
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snps,map-to-dma-channel = <0x2>;
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snps,route-avcp;
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};
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queue3 {
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snps,avb-algorithm;
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snps,map-to-dma-channel = <0x3>;
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snps,priority = <0xc>;
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};
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};
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mtl_tx_setup1: tx-queues-config {
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snps,tx-queues-to-use = <4>;
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queue0 {
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snps,dcb-algorithm;
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};
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queue1 {
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snps,dcb-algorithm;
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};
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queue2 {
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snps,avb-algorithm;
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snps,send_slope = <0x1000>;
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snps,idle_slope = <0x1000>;
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snps,high_credit = <0x3e800>;
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snps,low_credit = <0xffc18000>;
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};
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queue3 {
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snps,avb-algorithm;
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snps,send_slope = <0x1000>;
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snps,idle_slope = <0x1000>;
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snps,high_credit = <0x3e800>;
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snps,low_credit = <0xffc18000>;
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};
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};
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};
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&i2c18 {
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#address-cells = <1>;
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#size-cells = <0>;
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eeprom@52 {
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compatible = "giantec,gt24c256c", "atmel,24c256";
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reg = <0x52>;
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pagesize = <64>;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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mac_addr1: mac-addr@0 {
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reg = <0x0 0x6>;
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};
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};
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};
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};
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&pcie0 {
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iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
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<0x100 &pcie_smmu 0x1 0x1>,
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<0x208 &pcie_smmu 0x2 0x1>,
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<0x210 &pcie_smmu 0x3 0x1>,
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<0x218 &pcie_smmu 0x4 0x1>,
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<0x300 &pcie_smmu 0x5 0x1>,
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<0x400 &pcie_smmu 0x6 0x1>,
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<0x500 &pcie_smmu 0x7 0x1>,
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<0x501 &pcie_smmu 0x8 0x1>;
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};
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&pcieport0 {
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#address-cells = <3>;
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#size-cells = <2>;
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pcie@0,0 {
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compatible = "pci1179,0623";
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reg = <0x10000 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x2 0xff>;
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vddc-supply = <&vreg_0p9>;
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vdd18-supply = <&vreg_1p8>;
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vdd09-supply = <&vreg_0p9>;
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vddio1-supply = <&vreg_1p8>;
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vddio2-supply = <&vreg_1p8>;
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vddio18-supply = <&vreg_1p8>;
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i2c-parent = <&i2c18 0x77>;
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resx-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&tc9563_resx_n>;
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pinctrl-names = "default";
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pcie@1,0 {
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reg = <0x20800 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x3 0xff>;
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};
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pcie@2,0 {
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reg = <0x21000 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x4 0xff>;
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};
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pcie@3,0 {
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reg = <0x21800 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x5 0xff>;
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pci@0,0 {
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reg = <0x50000 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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};
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pci@0,1 {
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reg = <0x50100 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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};
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};
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};
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};
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&serdes1 {
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phy-supply = <&vreg_l5a>;
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status = "okay";
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};
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&tlmm {
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ethernet1_default: ethernet1-default-state {
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ethernet1-mdc-pins {
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pins = "gpio20";
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function = "emac1_mdc";
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drive-strength = <16>;
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bias-pull-up;
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};
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ethernet1-mdio-pins {
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pins = "gpio21";
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function = "emac1_mdio";
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drive-strength = <16>;
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bias-pull-up;
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};
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};
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tc9563_resx_n: tc9563-resx-state {
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pins = "gpio140";
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function = "gpio";
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bias-disable;
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/* Reset pin of tc9563 is active low hence set default
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* state of this pin to output-high.
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*/
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output-high;
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};
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};
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