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Merge branch 'pci/aspm'
* pci/aspm: PCI/ASPM: Fix L1 substate handling in aspm_attr_store_common() Revert "PCI/ASPM: Disable only ASPM_STATE_L1 when driver, disables L1" PCI/ASPM: Convert printk() to pr_*() and add include PCI/ASPM: Remove unnecessary includes PCI/ASPM: Use FIELD_MAX() instead of literals PCI/ASPM: Use time constants PCI/ASPM: Return U32_MAX instead of bit magic construct PCI/ASPM: Use FIELD_GET/PREP() to access PCIe capability fields PCI: Add PCI_L1SS_CTL2 fields
This commit is contained in:
Bjorn Helgaas
commit
b63c6dfe41
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@ -7,7 +7,9 @@
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* Copyright (C) Shaohua Li (shaohua.li@intel.com)
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*/
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#include <linux/bitfield.h>
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#include <linux/kernel.h>
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#include <linux/limits.h>
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#include <linux/math.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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@ -16,9 +18,10 @@
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#include <linux/errno.h>
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#include <linux/pm.h>
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#include <linux/init.h>
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#include <linux/printk.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <linux/delay.h>
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#include <linux/time.h>
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#include "../pci.h"
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#ifdef MODULE_PARAM_PREFIX
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@ -267,10 +270,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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/* Convert L0s latency encoding to ns */
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static u32 calc_l0s_latency(u32 lnkcap)
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{
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u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
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u32 encoding = FIELD_GET(PCI_EXP_LNKCAP_L0SEL, lnkcap);
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if (encoding == 0x7)
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return (5 * 1000); /* > 4us */
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return 5 * NSEC_PER_USEC; /* > 4us */
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return (64 << encoding);
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}
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@ -278,26 +281,26 @@ static u32 calc_l0s_latency(u32 lnkcap)
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static u32 calc_l0s_acceptable(u32 encoding)
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{
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if (encoding == 0x7)
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return -1U;
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return U32_MAX;
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return (64 << encoding);
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}
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/* Convert L1 latency encoding to ns */
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static u32 calc_l1_latency(u32 lnkcap)
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{
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u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
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u32 encoding = FIELD_GET(PCI_EXP_LNKCAP_L1EL, lnkcap);
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if (encoding == 0x7)
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return (65 * 1000); /* > 64us */
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return (1000 << encoding);
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return 65 * NSEC_PER_USEC; /* > 64us */
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return NSEC_PER_USEC << encoding;
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}
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/* Convert L1 acceptable latency encoding to ns */
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static u32 calc_l1_acceptable(u32 encoding)
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{
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if (encoding == 0x7)
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return -1U;
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return (1000 << encoding);
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return U32_MAX;
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return NSEC_PER_USEC << encoding;
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}
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/* Convert L1SS T_pwr encoding to usec */
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@ -325,33 +328,33 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)
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*/
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static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
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{
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u64 threshold_ns = (u64) threshold_us * 1000;
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u64 threshold_ns = (u64)threshold_us * NSEC_PER_USEC;
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/*
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* LTR_L1.2_THRESHOLD_Value ("value") is a 10-bit field with max
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* value of 0x3ff.
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*/
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if (threshold_ns <= 0x3ff * 1) {
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if (threshold_ns <= 1 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
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*scale = 0; /* Value times 1ns */
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*value = threshold_ns;
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} else if (threshold_ns <= 0x3ff * 32) {
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} else if (threshold_ns <= 32 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
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*scale = 1; /* Value times 32ns */
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*value = roundup(threshold_ns, 32) / 32;
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} else if (threshold_ns <= 0x3ff * 1024) {
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} else if (threshold_ns <= 1024 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
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*scale = 2; /* Value times 1024ns */
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*value = roundup(threshold_ns, 1024) / 1024;
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} else if (threshold_ns <= 0x3ff * 32768) {
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} else if (threshold_ns <= 32768 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
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*scale = 3; /* Value times 32768ns */
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*value = roundup(threshold_ns, 32768) / 32768;
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} else if (threshold_ns <= 0x3ff * 1048576) {
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} else if (threshold_ns <= 1048576 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
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*scale = 4; /* Value times 1048576ns */
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*value = roundup(threshold_ns, 1048576) / 1048576;
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} else if (threshold_ns <= 0x3ff * (u64) 33554432) {
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} else if (threshold_ns <= (u64)33554432 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
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*scale = 5; /* Value times 33554432ns */
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*value = roundup(threshold_ns, 33554432) / 33554432;
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} else {
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*scale = 5;
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*value = 0x3ff; /* Max representable value */
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*value = FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE);
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}
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}
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@ -371,11 +374,11 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
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link = endpoint->bus->self->link_state;
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/* Calculate endpoint L0s acceptable latency */
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encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L0S) >> 6;
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encoding = FIELD_GET(PCI_EXP_DEVCAP_L0S, endpoint->devcap);
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acceptable_l0s = calc_l0s_acceptable(encoding);
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/* Calculate endpoint L1 acceptable latency */
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encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L1) >> 9;
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encoding = FIELD_GET(PCI_EXP_DEVCAP_L1, endpoint->devcap);
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acceptable_l1 = calc_l1_acceptable(encoding);
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while (link) {
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@ -417,7 +420,7 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
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if ((link->aspm_capable & ASPM_STATE_L1) &&
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(latency + l1_switch_latency > acceptable_l1))
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link->aspm_capable &= ~ASPM_STATE_L1;
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l1_switch_latency += 1000;
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l1_switch_latency += NSEC_PER_USEC;
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link = link->parent;
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}
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@ -446,22 +449,24 @@ static void aspm_calc_l12_info(struct pcie_link_state *link,
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u32 pl1_2_enables, cl1_2_enables;
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/* Choose the greater of the two Port Common_Mode_Restore_Times */
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val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
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val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
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val1 = FIELD_GET(PCI_L1SS_CAP_CM_RESTORE_TIME, parent_l1ss_cap);
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val2 = FIELD_GET(PCI_L1SS_CAP_CM_RESTORE_TIME, child_l1ss_cap);
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t_common_mode = max(val1, val2);
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/* Choose the greater of the two Port T_POWER_ON times */
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val1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
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scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
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val2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
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scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
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val1 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_VALUE, parent_l1ss_cap);
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scale1 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_SCALE, parent_l1ss_cap);
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val2 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_VALUE, child_l1ss_cap);
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scale2 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_SCALE, child_l1ss_cap);
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if (calc_l12_pwron(parent, scale1, val1) >
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calc_l12_pwron(child, scale2, val2)) {
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ctl2 |= scale1 | (val1 << 3);
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ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale1) |
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FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_VALUE, val1);
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t_power_on = calc_l12_pwron(parent, scale1, val1);
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} else {
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ctl2 |= scale2 | (val2 << 3);
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ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale2) |
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FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_VALUE, val2);
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t_power_on = calc_l12_pwron(child, scale2, val2);
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}
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@ -477,7 +482,9 @@ static void aspm_calc_l12_info(struct pcie_link_state *link,
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*/
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l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
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encode_l12_threshold(l1_2_threshold, &scale, &value);
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ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
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ctl1 |= FIELD_PREP(PCI_L1SS_CTL1_CM_RESTORE_TIME, t_common_mode) |
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FIELD_PREP(PCI_L1SS_CTL1_LTR_L12_TH_VALUE, value) |
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FIELD_PREP(PCI_L1SS_CTL1_LTR_L12_TH_SCALE, scale);
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/* Some broken devices only support dword access to L1 SS */
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pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
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@ -1059,7 +1066,8 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
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if (state & PCIE_LINK_STATE_L0S)
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link->aspm_disable |= ASPM_STATE_L0S;
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if (state & PCIE_LINK_STATE_L1)
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link->aspm_disable |= ASPM_STATE_L1;
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/* L1 PM substates require L1 */
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link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
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if (state & PCIE_LINK_STATE_L1_1)
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link->aspm_disable |= ASPM_STATE_L1_1;
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if (state & PCIE_LINK_STATE_L1_2)
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@ -1247,6 +1255,8 @@ static ssize_t aspm_attr_store_common(struct device *dev,
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link->aspm_disable &= ~ASPM_STATE_L1;
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} else {
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link->aspm_disable |= state;
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if (state & ASPM_STATE_L1)
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link->aspm_disable |= ASPM_STATE_L1SS;
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}
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pcie_config_aspm_link(link, policy_to_aspm_state(link));
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@ -1361,10 +1371,10 @@ static int __init pcie_aspm_disable(char *str)
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aspm_policy = POLICY_DEFAULT;
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aspm_disabled = 1;
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aspm_support_enabled = false;
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printk(KERN_INFO "PCIe ASPM is disabled\n");
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pr_info("PCIe ASPM is disabled\n");
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} else if (!strcmp(str, "force")) {
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aspm_force = 1;
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printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
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pr_info("PCIe ASPM is forcibly enabled\n");
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}
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return 1;
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}
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@ -1088,6 +1088,8 @@
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#define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */
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#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
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#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
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#define PCI_L1SS_CTL2_T_PWR_ON_SCALE 0x00000003 /* T_POWER_ON Scale */
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#define PCI_L1SS_CTL2_T_PWR_ON_VALUE 0x000000f8 /* T_POWER_ON Value */
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/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
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#define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
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