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drm/i915/cmtg: Add hook to enable CMTG with sync to port

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Add a hook to enable CMTG by programming CMTG CTL with Sync to Port.
When CMTG starts running, the Sync to Port bit will be cleared. Add
a wait to check its running status and trigger WARN_ON() on timeout.

Bspec: 69088
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260615200339.885190-16-animesh.manna@intel.com
This commit is contained in:
Animesh Manna 2026-06-16 01:33:32 +05:30
parent a50f027636
commit b6261ac5d5
3 changed files with 29 additions and 6 deletions
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27
drivers/gpu/drm/i915/display/intel_cmtg.c
View File

@ -117,11 +117,11 @@ static void intel_cmtg_get_config(struct intel_display *display,
{
u32 val;
val = intel_de_read(display, TRANS_CMTG_CTL_A);
val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_A));
cmtg_config->cmtg_a_enable = val & CMTG_ENABLE;
if (intel_cmtg_has_cmtg_b(display)) {
val = intel_de_read(display, TRANS_CMTG_CTL_B);
val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_B));
cmtg_config->cmtg_b_enable = val & CMTG_ENABLE;
}
@ -154,14 +154,14 @@ static void intel_cmtg_disable(struct intel_display *display,
if (cmtg_config->cmtg_a_enable) {
drm_dbg_kms(display->drm, "Disabling CMTG A\n");
intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);
intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_A), CMTG_ENABLE, 0);
clk_sel_clr |= CMTG_CLK_SEL_A_MASK;
clk_sel_set |= CMTG_CLK_SEL_A_DISABLED;
}
if (cmtg_config->cmtg_b_enable) {
drm_dbg_kms(display->drm, "Disabling CMTG B\n");
intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);
intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_B), CMTG_ENABLE, 0);
clk_sel_clr |= CMTG_CLK_SEL_B_MASK;
clk_sel_set |= CMTG_CLK_SEL_B_DISABLED;
}
@ -291,3 +291,22 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
intel_de_write(display, PIPE_LINK_M1(display, cmtg_transcoder), m_n->link_m);
intel_de_write(display, PIPE_LINK_N1(display, cmtg_transcoder), m_n->link_n);
}
void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 cmtg_ctl;
if (!intel_cmtg_is_allowed(crtc_state))
return;
cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
CMTG_SYNC_TO_PORT, 50)) {
drm_WARN(display->drm, 1, "CMTG: %s enable timeout\n",
transcoder_name(cpu_transcoder));
}
}

1
drivers/gpu/drm/i915/display/intel_cmtg.h
View File

@ -16,6 +16,7 @@ enum set_timing_type {
LRR
};
void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);

7
drivers/gpu/drm/i915/display/intel_cmtg_regs.h
View File

@ -16,8 +16,11 @@
#define CMTG_CLK_SELECT_PHYB_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
#define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
#define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
#define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
#define _TRANS_CMTG_CTL_A 0x6fa88
#define _TRANS_CMTG_CTL_B 0x6fb88
#define TRANS_CMTG_CTL(trans) _MMIO_TRANS((trans), \
_TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
#define CMTG_ENABLE REG_BIT(31)
#define CMTG_SYNC_TO_PORT REG_BIT(29)
#endif /* __INTEL_CMTG_REGS_H__ */