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arm64: dts: freescale: Add NXP S32N79 SoC support
Add device tree support for the NXP S32N79 automotive SoC [1]. The S32N79 features eight Arm Cortex-A78AE cores organized in four dual-core clusters, with a three-level cache hierarchy (L1/L2 per core, L3 per dual-core cluster) and 32GB of DRAM memory. It includes an SMMUv3 for IOMMU functionality. On S32N79 SoC, peripherals are organized into subsystems, such as: - CIS (Coherent Interconnect Subsystem) - COSS (Connectivity Subsystem) - FSS (Foundation Subsystem) This initial support includes basic peripherals: - GICv3, SMMUv3 from CIS Subsystem - PL011 UARTs and IRQ steering controller from COSS Subsystem - uSDHC from FSS Subsystem Clock and Pin multiplexing settings for the chip are managed over SCMI. [1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32n-vehicle-super-integration-processors:S32N Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Co-developed-by: Andra-Teodora Ilie <andra.ilie@nxp.com> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com> Co-developed-by: Andrei Cherechesu <andrei.cherechesu@nxp.com> Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Ciprian Marian Costea
Frank Li
parent
ca2932ae84
commit
b621908301
362
arch/arm64/boot/dts/freescale/s32n79.dtsi
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362
arch/arm64/boot/dts/freescale/s32n79.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* NXP S32N79 SoC
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*
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* Copyright 2026 NXP
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cis-bus {
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compatible = "simple-bus";
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ranges = <0x4f200000 0x0 0x4f200000 0xc00000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gic: interrupt-controller@4f200000 {
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compatible = "arm,gic-v3";
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reg = <0x4f200000 0x10000>, /* GIC Dist */
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<0x4f260000 0x100000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* GICR (RD_base + SGI_base) */
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ranges;
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its: msi-controller@4f240000 {
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compatible = "arm,gic-v3-its";
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reg = <0x4f240000 0x20000>;
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#msi-cells = <1>;
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msi-controller;
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};
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};
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smmu: iommu@4fc00000 {
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compatible = "arm,smmu-v3";
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reg = <0x4fc00000 0x200000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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#iommu-cells = <1>;
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dma-coherent;
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status = "disabled";
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};
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};
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coss-bus {
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compatible = "simple-bus";
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ranges = <0x4a000000 0x0 0x4a000000 0xff0000>,
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<0x4e000000 0x0 0x4e000000 0x1000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@4a030000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x4a030000 0x1000>;
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interrupt-parent = <&irqsteer_coss>;
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interrupts = <264>;
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clocks = <&clks 0x9a>, <&clks 0x9a>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart5: serial@4a060000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x4a060000 0x1000>;
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interrupt-parent = <&irqsteer_coss>;
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interrupts = <269>;
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clocks = <&clks 0x9a>, <&clks 0x9a>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart6: serial@4aa30000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x4aa30000 0x1000>;
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interrupt-parent = <&irqsteer_coss>;
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interrupts = <270>;
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clocks = <&clks 0x9a>, <&clks 0x9a>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart7: serial@4aa40000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x4aa40000 0x1000>;
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interrupt-parent = <&irqsteer_coss>;
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interrupts = <271>;
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clocks = <&clks 0x9a>, <&clks 0x9a>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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irqsteer_coss: interrupt-controller@4ed00000 {
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compatible = "nxp,s32n79-irqsteer";
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reg = <0x4ed00000 0x10000>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 0x9a>;
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clock-names = "ipg";
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fsl,channel = <0>;
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fsl,num-irqs = <512>;
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status = "disabled";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&cpu6>;
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};
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core1 {
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cpu = <&cpu7>;
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};
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};
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};
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l2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-size = <524288>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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l2_1: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-size = <524288>;
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cache-unified;
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next-level-cache = <&l3_1>;
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};
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l2_2: l2-cache2 {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-size = <524288>;
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cache-unified;
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next-level-cache = <&l3_2>;
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};
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l2_3: l2-cache3 {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-size = <524288>;
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cache-unified;
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next-level-cache = <&l3_3>;
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};
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l3_0: l3-cache0 {
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compatible = "cache";
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cache-level = <3>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-size = <1048576>;
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cache-unified;
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};
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l3_1: l3-cache1 {
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compatible = "cache";
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cache-level = <3>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-size = <1048576>;
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cache-unified;
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};
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l3_2: l3-cache2 {
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compatible = "cache";
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cache-level = <3>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-size = <1048576>;
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cache-unified;
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};
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l3_3: l3-cache3 {
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compatible = "cache";
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cache-level = <3>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-size = <1048576>;
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cache-unified;
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a78ae";
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reg = <0x0>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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};
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cpu1: cpu@100 {
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compatible = "arm,cortex-a78ae";
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reg = <0x100>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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};
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cpu2: cpu@10000 {
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compatible = "arm,cortex-a78ae";
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reg = <0x10000>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2_1>;
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};
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cpu3: cpu@10100 {
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compatible = "arm,cortex-a78ae";
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reg = <0x10100>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2_1>;
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};
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cpu4: cpu@20000 {
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compatible = "arm,cortex-a78ae";
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reg = <0x20000>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2_2>;
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};
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cpu5: cpu@20100 {
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compatible = "arm,cortex-a78ae";
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reg = <0x20100>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2_2>;
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};
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cpu6: cpu@30000 {
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compatible = "arm,cortex-a78ae";
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reg = <0x30000>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2_3>;
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};
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cpu7: cpu@30100 {
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compatible = "arm,cortex-a78ae";
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reg = <0x30100>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&l2_3>;
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};
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};
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firmware {
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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scmi: scmi {
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compatible = "arm,scmi-smc";
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#address-cells = <1>;
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#size-cells = <0>;
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shmem = <&scmi_shbuf>;
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arm,smc-id = <0xc20000fe>;
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status = "okay";
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clks: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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fss-bus {
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compatible = "simple-bus";
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ranges = <0x5b490000 0x0 0x5b490000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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usdhc0: mmc@5b490000 {
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compatible = "nxp,s32n79-usdhc";
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reg = <0x5b490000 0x1000>;
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interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <8>;
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status = "disabled";
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};
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};
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pmu: pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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