From 07bab7b81d8a4de604ae4175978adf37137c35d6 Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Mon, 23 Jun 2025 23:46:27 +0200 Subject: [PATCH 1/4] dt-bindings: clock: rp1: Add missing MIPI DSI defines Declare the positional index for the RP1 MIPI clocks. Signed-off-by: Andrea della Porta Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/c20066500908db854aa4816b40e956296bab526a.1750714412.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- include/dt-bindings/clock/raspberrypi,rp1-clocks.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/raspberrypi,rp1-clocks.h b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h index 248efb895f35..7915fb8197bf 100644 --- a/include/dt-bindings/clock/raspberrypi,rp1-clocks.h +++ b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h @@ -58,4 +58,8 @@ #define RP1_PLL_VIDEO_PRI_PH 43 #define RP1_PLL_AUDIO_TERN 44 +/* MIPI clocks managed by the DSI driver */ +#define RP1_CLK_MIPI0_DSI_BYTECLOCK 45 +#define RP1_CLK_MIPI1_DSI_BYTECLOCK 46 + #endif From a7713a7dd15962c077527eea9a2f56d821ca4a1d Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Mon, 23 Jun 2025 23:46:28 +0200 Subject: [PATCH 2/4] clk: rp1: Implement remaining clock tree The RP1 clock generator driver currently defines only the fundamental clocks such as the front PLLs for system, audio and video subsystems and the ethernet clock. Add the remaining clocks to the tree so as to be completed, which means that the following RP1 peripherals could now consume their specific clocks and be enabled to work (provided that the relevant driver changes for each specific peripheral, if any, are committed): - ADC - Audio IN/OUT - DMA controller - I2S - MIPI DPI/DSI - PWM - SDIO - UART - Video Encoder Signed-off-by: Andrea della Porta Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/17e5c6e0c085cfa0bf4b63b639cdc92c6a4c1418.1750714412.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- drivers/clk/clk-rp1.c | 976 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 968 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk-rp1.c b/drivers/clk/clk-rp1.c index afff90d48734..e8f264d7f34e 100644 --- a/drivers/clk/clk-rp1.c +++ b/drivers/clk/clk-rp1.c @@ -368,6 +368,11 @@ struct rp1_clk_desc { struct clk_divider div; }; +static struct rp1_clk_desc *clk_audio_core; +static struct rp1_clk_desc *clk_audio; +static struct rp1_clk_desc *clk_i2s; +static struct clk_hw *clk_xosc; + static inline void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val) { @@ -475,7 +480,6 @@ static int rp1_pll_core_set_rate(struct clk_hw *hw, struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; - unsigned long calc_rate; u32 fbdiv_int, fbdiv_frac; /* Disable dividers to start with. */ @@ -484,8 +488,8 @@ static int rp1_pll_core_set_rate(struct clk_hw *hw, clockman_write(clockman, data->fbdiv_frac_reg, 0); spin_unlock(&clockman->regs_lock); - calc_rate = get_pll_core_divider(hw, rate, parent_rate, - &fbdiv_int, &fbdiv_frac); + get_pll_core_divider(hw, rate, parent_rate, + &fbdiv_int, &fbdiv_frac); spin_lock(&clockman->regs_lock); clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); @@ -497,8 +501,6 @@ static int rp1_pll_core_set_rate(struct clk_hw *hw, if (WARN_ON_ONCE(parent_rate > (rate / 16))) return -ERANGE; - pll_core->cached_rate = calc_rate; - spin_lock(&clockman->regs_lock); /* Don't need to divide ref unless parent_rate > (output freq / 16) */ clockman_write(clockman, data->cs_reg, @@ -617,8 +619,12 @@ static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw, static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { + struct clk_hw *clk_audio_hw = &clk_audio->hw; u32 div1, div2; + if (hw == clk_audio_hw && clk_audio->cached_rate == rate) + *parent_rate = clk_audio_core->cached_rate; + get_pll_prim_dividers(rate, *parent_rate, &div1, &div2); return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2); @@ -964,6 +970,59 @@ static int rp1_clock_set_rate(struct clk_hw *hw, unsigned long rate, return rp1_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff); } +static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw, + unsigned long target_rate, + int *pdiv_prim, int *pdiv_clk) +{ + static const int prim_divs[] = { + 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, 16, + 18, 20, 21, 24, 25, 28, 30, 35, 36, 42, 49, + }; + const unsigned long xosc_rate = clk_hw_get_rate(clk_xosc); + const unsigned long core_min = xosc_rate * 16; + const unsigned long core_max = 2400000000; + int best_div_prim = 1, best_div_clk = 1; + unsigned long best_rate = core_max + 1; + unsigned long core_rate = 0; + int div_int, div_frac; + u64 div; + int i; + + /* Given the target rate, choose a set of divisors/multipliers */ + for (i = 0; i < ARRAY_SIZE(prim_divs); i++) { + int div_prim = prim_divs[i]; + int div_clk; + + for (div_clk = 1; div_clk <= 256; div_clk++) { + core_rate = target_rate * div_clk * div_prim; + if (core_rate >= core_min) { + if (core_rate < best_rate) { + best_rate = core_rate; + best_div_prim = div_prim; + best_div_clk = div_clk; + } + break; + } + } + } + + if (best_rate < core_max) { + div = ((best_rate << 24) + xosc_rate / 2) / xosc_rate; + div_int = div >> 24; + div_frac = div % (1 << 24); + core_rate = (xosc_rate * ((div_int << 24) + div_frac) + (1 << 23)) >> 24; + } else { + core_rate = 0; + } + + if (pdiv_prim) + *pdiv_prim = best_div_prim; + if (pdiv_clk) + *pdiv_clk = best_div_clk; + + return core_rate; +} + static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, int parent_idx, unsigned long rate, @@ -972,12 +1031,35 @@ static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, { struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); const struct rp1_clock_data *data = clock->data; + struct clk_hw *clk_audio_hw = &clk_audio->hw; + struct clk_hw *clk_i2s_hw = &clk_i2s->hw; struct clk_hw *parent; u32 div; u64 tmp; parent = clk_hw_get_parent_by_index(hw, parent_idx); + if (hw == clk_i2s_hw && clk_i2s->cached_rate == rate && parent == clk_audio_hw) { + *prate = clk_audio->cached_rate; + *calc_rate = rate; + return; + } + + if (hw == clk_i2s_hw && parent == clk_audio_hw) { + unsigned long core_rate, audio_rate, i2s_rate; + int div_prim, div_clk; + + core_rate = calc_core_pll_rate(parent, rate, &div_prim, &div_clk); + audio_rate = DIV_ROUND_CLOSEST(core_rate, div_prim); + i2s_rate = DIV_ROUND_CLOSEST(audio_rate, div_clk); + clk_audio_core->cached_rate = core_rate; + clk_audio->cached_rate = audio_rate; + clk_i2s->cached_rate = i2s_rate; + *prate = audio_rate; + *calc_rate = i2s_rate; + return; + } + *prate = clk_hw_get_rate(parent); div = rp1_clock_choose_div(rate, *prate, data); @@ -1062,6 +1144,34 @@ static int rp1_clock_determine_rate(struct clk_hw *hw, return 0; } +static int rp1_varsrc_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + + /* + * "varsrc" exists purely to let clock dividers know the frequency + * of an externally-managed clock source (such as MIPI DSI byte-clock) + * which may change at run-time as a side-effect of some other driver. + */ + clock->cached_rate = rate; + return 0; +} + +static unsigned long rp1_varsrc_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + + return clock->cached_rate; +} + +static long rp1_varsrc_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return rate; +} + static const struct clk_ops rp1_pll_core_ops = { .is_prepared = rp1_pll_core_is_on, .prepare = rp1_pll_core_on, @@ -1106,6 +1216,12 @@ static const struct clk_ops rp1_clk_ops = { .determine_rate = rp1_clock_determine_rate, }; +static const struct clk_ops rp1_varsrc_ops = { + .set_rate = rp1_varsrc_set_rate, + .recalc_rate = rp1_varsrc_recalc_rate, + .round_rate = rp1_varsrc_round_rate, +}; + static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman, struct rp1_clk_desc *desc) { @@ -1241,6 +1357,36 @@ static struct rp1_clk_desc pll_sys_desc = REGISTER_PLL( ) ); +static struct rp1_clk_desc pll_audio_desc = REGISTER_PLL( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio", + (const struct clk_parent_data[]) { + { .hw = &pll_audio_core_desc.hw } + }, + &rp1_pll_ops, + CLK_SET_RATE_PARENT + ), + CLK_DATA(rp1_pll_data, + .ctrl_reg = PLL_AUDIO_PRIM, + .fc0_src = FC_NUM(4, 2), + ) +); + +static struct rp1_clk_desc pll_video_desc = REGISTER_PLL( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video", + (const struct clk_parent_data[]) { + { .hw = &pll_video_core_desc.hw } + }, + &rp1_pll_ops, + 0 + ), + CLK_DATA(rp1_pll_data, + .ctrl_reg = PLL_VIDEO_PRIM, + .fc0_src = FC_NUM(3, 2), + ) +); + static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV( .hw.init = CLK_HW_INIT_PARENTS_DATA( "pll_sys_sec", @@ -1256,16 +1402,42 @@ static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV( ) ); +static struct rp1_clk_desc pll_video_sec_desc = REGISTER_PLL_DIV( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video_sec", + (const struct clk_parent_data[]) { + { .hw = &pll_video_core_desc.hw } + }, + &rp1_pll_divider_ops, + 0 + ), + CLK_DATA(rp1_pll_data, + .ctrl_reg = PLL_VIDEO_SEC, + .fc0_src = FC_NUM(5, 3), + ) +); + +static const struct clk_parent_data clk_eth_tsu_parents[] = { + { .index = 0 }, + { .hw = &pll_video_sec_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, +}; + static struct rp1_clk_desc clk_eth_tsu_desc = REGISTER_CLK( .hw.init = CLK_HW_INIT_PARENTS_DATA( "clk_eth_tsu", - (const struct clk_parent_data[]) { { .index = 0 } }, + clk_eth_tsu_parents, &rp1_clk_ops, 0 ), CLK_DATA(rp1_clock_data, .num_std_parents = 0, - .num_aux_parents = 1, + .num_aux_parents = 8, .ctrl_reg = CLK_ETH_TSU_CTRL, .div_int_reg = CLK_ETH_TSU_DIV_INT, .sel_reg = CLK_ETH_TSU_SEL, @@ -1278,6 +1450,7 @@ static struct rp1_clk_desc clk_eth_tsu_desc = REGISTER_CLK( static const struct clk_parent_data clk_eth_parents[] = { { .hw = &pll_sys_sec_desc.div.hw }, { .hw = &pll_sys_desc.hw }, + { .hw = &pll_video_sec_desc.hw }, }; static struct rp1_clk_desc clk_eth_desc = REGISTER_CLK( @@ -1289,7 +1462,7 @@ static struct rp1_clk_desc clk_eth_desc = REGISTER_CLK( ), CLK_DATA(rp1_clock_data, .num_std_parents = 0, - .num_aux_parents = 2, + .num_aux_parents = 3, .ctrl_reg = CLK_ETH_CTRL, .div_int_reg = CLK_ETH_DIV_INT, .sel_reg = CLK_ETH_SEL, @@ -1342,6 +1515,756 @@ static struct rp1_clk_desc pll_sys_pri_ph_desc = REGISTER_PLL( ) ); +static struct rp1_clk_desc pll_audio_pri_ph_desc = REGISTER_PLL( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_pri_ph", + (const struct clk_parent_data[]) { + { .hw = &pll_audio_desc.hw } + }, + &rp1_pll_ph_ops, + 0 + ), + CLK_DATA(rp1_pll_ph_data, + .ph_reg = PLL_AUDIO_PRIM, + .fixed_divider = 2, + .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(5, 1), + ) +); + +static struct rp1_clk_desc pll_video_pri_ph_desc = REGISTER_PLL( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video_pri_ph", + (const struct clk_parent_data[]) { + { .hw = &pll_video_desc.hw } + }, + &rp1_pll_ph_ops, + 0 + ), + CLK_DATA(rp1_pll_ph_data, + .ph_reg = PLL_VIDEO_PRIM, + .fixed_divider = 2, + .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(4, 3), + ) +); + +static struct rp1_clk_desc pll_audio_sec_desc = REGISTER_PLL_DIV( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_sec", + (const struct clk_parent_data[]) { + { .hw = &pll_audio_core_desc.hw } + }, + &rp1_pll_divider_ops, + 0 + ), + CLK_DATA(rp1_pll_data, + .ctrl_reg = PLL_AUDIO_SEC, + .fc0_src = FC_NUM(6, 2), + ) +); + +static struct rp1_clk_desc pll_audio_tern_desc = REGISTER_PLL_DIV( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_tern", + (const struct clk_parent_data[]) { + { .hw = &pll_audio_core_desc.hw } + }, + &rp1_pll_divider_ops, + 0 + ), + CLK_DATA(rp1_pll_data, + .ctrl_reg = PLL_AUDIO_TERN, + .fc0_src = FC_NUM(6, 2), + ) +); + +static struct rp1_clk_desc clk_slow_sys_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_slow_sys", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_clk_ops, + CLK_IS_CRITICAL + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 1, + .num_aux_parents = 0, + .ctrl_reg = CLK_SLOW_SYS_CTRL, + .div_int_reg = CLK_SLOW_SYS_DIV_INT, + .sel_reg = CLK_SLOW_SYS_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(1, 4), + .clk_src_mask = 0x1, + ) +); + +static const struct clk_parent_data clk_dma_parents[] = { + { .hw = &pll_sys_pri_ph_desc.hw }, + { .hw = &pll_video_desc.hw }, + { .index = 0 }, +}; + +static struct rp1_clk_desc clk_dma_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_dma", + clk_dma_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 3, + .ctrl_reg = CLK_DMA_CTRL, + .div_int_reg = CLK_DMA_DIV_INT, + .sel_reg = CLK_DMA_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(2, 2), + ) +); + +static const struct clk_parent_data clk_uart_parents[] = { + { .hw = &pll_sys_pri_ph_desc.hw }, + { .hw = &pll_video_desc.hw }, + { .index = 0 }, +}; + +static struct rp1_clk_desc clk_uart_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_uart", + clk_uart_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 3, + .ctrl_reg = CLK_UART_CTRL, + .div_int_reg = CLK_UART_DIV_INT, + .sel_reg = CLK_UART_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(6, 7), + ) +); + +static const struct clk_parent_data clk_pwm0_parents[] = { + { .index = -1 }, + { .hw = &pll_video_sec_desc.hw }, + { .index = 0 }, +}; + +static struct rp1_clk_desc clk_pwm0_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_pwm0", + clk_pwm0_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 3, + .ctrl_reg = CLK_PWM0_CTRL, + .div_int_reg = CLK_PWM0_DIV_INT, + .div_frac_reg = CLK_PWM0_DIV_FRAC, + .sel_reg = CLK_PWM0_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 76800 * HZ_PER_KHZ, + .fc0_src = FC_NUM(0, 5), + ) +); + +static const struct clk_parent_data clk_pwm1_parents[] = { + { .index = -1 }, + { .hw = &pll_video_sec_desc.hw }, + { .index = 0 }, +}; + +static struct rp1_clk_desc clk_pwm1_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_pwm1", + clk_pwm1_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 3, + .ctrl_reg = CLK_PWM1_CTRL, + .div_int_reg = CLK_PWM1_DIV_INT, + .div_frac_reg = CLK_PWM1_DIV_FRAC, + .sel_reg = CLK_PWM1_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 76800 * HZ_PER_KHZ, + .fc0_src = FC_NUM(1, 5), + ) +); + +static const struct clk_parent_data clk_audio_in_parents[] = { + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &pll_video_sec_desc.hw }, + { .index = 0 }, +}; + +static struct rp1_clk_desc clk_audio_in_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_audio_in", + clk_audio_in_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 5, + .ctrl_reg = CLK_AUDIO_IN_CTRL, + .div_int_reg = CLK_AUDIO_IN_DIV_INT, + .sel_reg = CLK_AUDIO_IN_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 76800 * HZ_PER_KHZ, + .fc0_src = FC_NUM(2, 5), + ) +); + +static const struct clk_parent_data clk_audio_out_parents[] = { + { .index = -1 }, + { .index = -1 }, + { .hw = &pll_video_sec_desc.hw }, + { .index = 0 }, +}; + +static struct rp1_clk_desc clk_audio_out_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_audio_out", + clk_audio_out_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 4, + .ctrl_reg = CLK_AUDIO_OUT_CTRL, + .div_int_reg = CLK_AUDIO_OUT_DIV_INT, + .sel_reg = CLK_AUDIO_OUT_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 153600 * HZ_PER_KHZ, + .fc0_src = FC_NUM(3, 5), + ) +); + +static const struct clk_parent_data clk_i2s_parents[] = { + { .index = 0 }, + { .hw = &pll_audio_desc.hw }, + { .hw = &pll_audio_sec_desc.hw }, +}; + +static struct rp1_clk_desc clk_i2s_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_i2s", + clk_i2s_parents, + &rp1_clk_ops, + CLK_SET_RATE_PARENT + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 3, + .ctrl_reg = CLK_I2S_CTRL, + .div_int_reg = CLK_I2S_DIV_INT, + .sel_reg = CLK_I2S_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 4), + ) +); + +static struct rp1_clk_desc clk_mipi0_cfg_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi0_cfg", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_MIPI0_CFG_CTRL, + .div_int_reg = CLK_MIPI0_CFG_DIV_INT, + .sel_reg = CLK_MIPI0_CFG_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 5), + ) +); + +static struct rp1_clk_desc clk_mipi1_cfg_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi1_cfg", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_MIPI1_CFG_CTRL, + .div_int_reg = CLK_MIPI1_CFG_DIV_INT, + .sel_reg = CLK_MIPI1_CFG_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 6), + .clk_src_mask = 0x1, + ) +); + +static struct rp1_clk_desc clk_adc_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_adc", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_ADC_CTRL, + .div_int_reg = CLK_ADC_DIV_INT, + .sel_reg = CLK_ADC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 5), + ) +); + +static struct rp1_clk_desc clk_sdio_timer_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_sdio_timer", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_SDIO_TIMER_CTRL, + .div_int_reg = CLK_SDIO_TIMER_DIV_INT, + .sel_reg = CLK_SDIO_TIMER_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(3, 4), + ) +); + +static struct rp1_clk_desc clk_sdio_alt_src_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_sdio_alt_src", + (const struct clk_parent_data[]) { + { .hw = &pll_sys_desc.hw } + }, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_SDIO_ALT_SRC_CTRL, + .div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT, + .sel_reg = CLK_SDIO_ALT_SRC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 4), + ) +); + +static const struct clk_parent_data clk_dpi_parents[] = { + { .hw = &pll_sys_desc.hw }, + { .hw = &pll_video_sec_desc.hw }, + { .hw = &pll_video_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, +}; + +static struct rp1_clk_desc clk_dpi_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_dpi", + clk_dpi_parents, + &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let DPI driver set parent */ + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = VIDEO_CLK_DPI_CTRL, + .div_int_reg = VIDEO_CLK_DPI_DIV_INT, + .sel_reg = VIDEO_CLK_DPI_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(1, 6), + ) +); + +static const struct clk_parent_data clk_gp0_parents[] = { + { .index = 0 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &pll_sys_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &clk_i2s_desc.hw }, + { .hw = &clk_adc_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &clk_sys_desc.hw }, +}; + +static struct rp1_clk_desc clk_gp0_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp0", + clk_gp0_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 16, + .oe_mask = BIT(0), + .ctrl_reg = CLK_GP0_CTRL, + .div_int_reg = CLK_GP0_DIV_INT, + .div_frac_reg = CLK_GP0_DIV_FRAC, + .sel_reg = CLK_GP0_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 1), + ) +); + +static const struct clk_parent_data clk_gp1_parents[] = { + { .hw = &clk_sdio_timer_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &pll_sys_pri_ph_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &clk_adc_desc.hw }, + { .hw = &clk_dpi_desc.hw }, + { .hw = &clk_pwm0_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, +}; + +static struct rp1_clk_desc clk_gp1_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp1", + clk_gp1_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 16, + .oe_mask = BIT(1), + .ctrl_reg = CLK_GP1_CTRL, + .div_int_reg = CLK_GP1_DIV_INT, + .div_frac_reg = CLK_GP1_DIV_FRAC, + .sel_reg = CLK_GP1_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(1, 1), + ) +); + +static struct rp1_clk_desc clksrc_mipi0_dsi_byteclk_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clksrc_mipi0_dsi_byteclk", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_varsrc_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 1, + .num_aux_parents = 0, + ) +); + +static struct rp1_clk_desc clksrc_mipi1_dsi_byteclk_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clksrc_mipi1_dsi_byteclk", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_varsrc_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 1, + .num_aux_parents = 0, + ) +); + +static const struct clk_parent_data clk_mipi0_dpi_parents[] = { + { .hw = &pll_sys_desc.hw }, + { .hw = &pll_video_sec_desc.hw }, + { .hw = &pll_video_desc.hw }, + { .hw = &clksrc_mipi0_dsi_byteclk_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, +}; + +static struct rp1_clk_desc clk_mipi0_dpi_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi0_dpi", + clk_mipi0_dpi_parents, + &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL, + .div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT, + .div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC, + .sel_reg = VIDEO_CLK_MIPI0_DPI_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(2, 6), + ) +); + +static const struct clk_parent_data clk_mipi1_dpi_parents[] = { + { .hw = &pll_sys_desc.hw }, + { .hw = &pll_video_sec_desc.hw }, + { .hw = &pll_video_desc.hw }, + { .hw = &clksrc_mipi1_dsi_byteclk_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, +}; + +static struct rp1_clk_desc clk_mipi1_dpi_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi1_dpi", + clk_mipi1_dpi_parents, + &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL, + .div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT, + .div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC, + .sel_reg = VIDEO_CLK_MIPI1_DPI_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(3, 6), + ) +); + +static const struct clk_parent_data clk_gp2_parents[] = { + { .hw = &clk_sdio_alt_src_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &pll_sys_sec_desc.hw }, + { .index = -1 }, + { .hw = &pll_video_desc.hw }, + { .hw = &clk_audio_in_desc.hw }, + { .hw = &clk_dpi_desc.hw }, + { .hw = &clk_pwm0_desc.hw }, + { .hw = &clk_pwm1_desc.hw }, + { .hw = &clk_mipi0_dpi_desc.hw }, + { .hw = &clk_mipi1_cfg_desc.hw }, + { .hw = &clk_sys_desc.hw }, +}; + +static struct rp1_clk_desc clk_gp2_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp2", + clk_gp2_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 16, + .oe_mask = BIT(2), + .ctrl_reg = CLK_GP2_CTRL, + .div_int_reg = CLK_GP2_DIV_INT, + .div_frac_reg = CLK_GP2_DIV_FRAC, + .sel_reg = CLK_GP2_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(2, 1), + ) +); + +static const struct clk_parent_data clk_gp3_parents[] = { + { .index = 0 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &pll_video_pri_ph_desc.hw }, + { .hw = &clk_audio_out_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .hw = &clk_mipi1_dpi_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, +}; + +static struct rp1_clk_desc clk_gp3_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp3", + clk_gp3_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 16, + .oe_mask = BIT(3), + .ctrl_reg = CLK_GP3_CTRL, + .div_int_reg = CLK_GP3_DIV_INT, + .div_frac_reg = CLK_GP3_DIV_FRAC, + .sel_reg = CLK_GP3_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(3, 1), + ) +); + +static const struct clk_parent_data clk_gp4_parents[] = { + { .index = 0 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &pll_video_sec_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &clk_mipi0_cfg_desc.hw }, + { .hw = &clk_uart_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .hw = &clk_sys_desc.hw }, +}; + +static struct rp1_clk_desc clk_gp4_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp4", + clk_gp4_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 16, + .oe_mask = BIT(4), + .ctrl_reg = CLK_GP4_CTRL, + .div_int_reg = CLK_GP4_DIV_INT, + .div_frac_reg = CLK_GP4_DIV_FRAC, + .sel_reg = CLK_GP4_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 1), + ) +); + +static const struct clk_parent_data clk_vec_parents[] = { + { .hw = &pll_sys_pri_ph_desc.hw }, + { .hw = &pll_video_sec_desc.hw }, + { .hw = &pll_video_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, +}; + +static struct rp1_clk_desc clk_vec_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_vec", + clk_vec_parents, + &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let VEC driver set parent */ + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = VIDEO_CLK_VEC_CTRL, + .div_int_reg = VIDEO_CLK_VEC_DIV_INT, + .sel_reg = VIDEO_CLK_VEC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 108 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 6), + ) +); + +static const struct clk_parent_data clk_gp5_parents[] = { + { .index = 0 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .hw = &pll_video_sec_desc.hw }, + { .hw = &clk_eth_tsu_desc.hw }, + { .index = -1 }, + { .hw = &clk_vec_desc.hw }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, + { .index = -1 }, +}; + +static struct rp1_clk_desc clk_gp5_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp5", + clk_gp5_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 16, + .oe_mask = BIT(5), + .ctrl_reg = CLK_GP5_CTRL, + .div_int_reg = CLK_GP5_DIV_INT, + .div_frac_reg = CLK_GP5_DIV_FRAC, + .sel_reg = CLK_GP5_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 1), + ) +); + static struct rp1_clk_desc *const clk_desc_array[] = { [RP1_PLL_SYS_CORE] = &pll_sys_core_desc, [RP1_PLL_AUDIO_CORE] = &pll_audio_core_desc, @@ -1352,6 +2275,38 @@ static struct rp1_clk_desc *const clk_desc_array[] = { [RP1_CLK_SYS] = &clk_sys_desc, [RP1_PLL_SYS_PRI_PH] = &pll_sys_pri_ph_desc, [RP1_PLL_SYS_SEC] = &pll_sys_sec_desc, + [RP1_PLL_AUDIO] = &pll_audio_desc, + [RP1_PLL_VIDEO] = &pll_video_desc, + [RP1_PLL_AUDIO_PRI_PH] = &pll_audio_pri_ph_desc, + [RP1_PLL_VIDEO_PRI_PH] = &pll_video_pri_ph_desc, + [RP1_PLL_AUDIO_SEC] = &pll_audio_sec_desc, + [RP1_PLL_VIDEO_SEC] = &pll_video_sec_desc, + [RP1_PLL_AUDIO_TERN] = &pll_audio_tern_desc, + [RP1_CLK_SLOW_SYS] = &clk_slow_sys_desc, + [RP1_CLK_DMA] = &clk_dma_desc, + [RP1_CLK_UART] = &clk_uart_desc, + [RP1_CLK_PWM0] = &clk_pwm0_desc, + [RP1_CLK_PWM1] = &clk_pwm1_desc, + [RP1_CLK_AUDIO_IN] = &clk_audio_in_desc, + [RP1_CLK_AUDIO_OUT] = &clk_audio_out_desc, + [RP1_CLK_I2S] = &clk_i2s_desc, + [RP1_CLK_MIPI0_CFG] = &clk_mipi0_cfg_desc, + [RP1_CLK_MIPI1_CFG] = &clk_mipi1_cfg_desc, + [RP1_CLK_ADC] = &clk_adc_desc, + [RP1_CLK_SDIO_TIMER] = &clk_sdio_timer_desc, + [RP1_CLK_SDIO_ALT_SRC] = &clk_sdio_alt_src_desc, + [RP1_CLK_GP0] = &clk_gp0_desc, + [RP1_CLK_GP1] = &clk_gp1_desc, + [RP1_CLK_GP2] = &clk_gp2_desc, + [RP1_CLK_GP3] = &clk_gp3_desc, + [RP1_CLK_GP4] = &clk_gp4_desc, + [RP1_CLK_GP5] = &clk_gp5_desc, + [RP1_CLK_VEC] = &clk_vec_desc, + [RP1_CLK_DPI] = &clk_dpi_desc, + [RP1_CLK_MIPI0_DPI] = &clk_mipi0_dpi_desc, + [RP1_CLK_MIPI1_DPI] = &clk_mipi1_dpi_desc, + [RP1_CLK_MIPI0_DSI_BYTECLOCK] = &clksrc_mipi0_dsi_byteclk_desc, + [RP1_CLK_MIPI1_DSI_BYTECLOCK] = &clksrc_mipi1_dsi_byteclk_desc, }; static const struct regmap_range rp1_reg_ranges[] = { @@ -1466,6 +2421,11 @@ static int rp1_clk_probe(struct platform_device *pdev) hws[i] = desc->clk_register(clockman, desc); } + clk_audio_core = &pll_audio_core_desc; + clk_audio = &pll_audio_desc; + clk_i2s = &clk_i2s_desc; + clk_xosc = clk_hw_get_parent_by_index(&clk_i2s->hw, 0); + platform_set_drvdata(pdev, clockman); return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, From 2d503aafdf70357e279ffef42ae18474328cc223 Mon Sep 17 00:00:00 2001 From: Akhilesh Patil Date: Sat, 19 Jul 2025 16:44:27 +0530 Subject: [PATCH 3/4] drivers: firmware: bcm47xx_sprom: fix spelling Fix spelling in bcm47xx_sprom.c as follows, specififc --> specific Signed-off-by: Akhilesh Patil Link: https://lore.kernel.org/r/aHt+Ey5AQ0dsCuB4@bhairav-test.ee.iitb.ac.in Signed-off-by: Florian Fainelli --- drivers/firmware/broadcom/bcm47xx_sprom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/broadcom/bcm47xx_sprom.c b/drivers/firmware/broadcom/bcm47xx_sprom.c index 14fbcd11657c..fdcd3a07abcd 100644 --- a/drivers/firmware/broadcom/bcm47xx_sprom.c +++ b/drivers/firmware/broadcom/bcm47xx_sprom.c @@ -404,7 +404,7 @@ static void bcm47xx_sprom_fill_auto(struct ssb_sprom *sprom, ENTRY(0x00000700, u8, pre, "noiselvl5gua1", noiselvl5gua[1], 0, fb); ENTRY(0x00000700, u8, pre, "noiselvl5gua2", noiselvl5gua[2], 0, fb); } -#undef ENTRY /* It's specififc, uses local variable, don't use it (again). */ +#undef ENTRY /* It's specific, uses local variable, don't use it (again). */ static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom, const char *prefix, bool fallback) From 41c9570e41783648ff9455ea903615406b2bb127 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Thu, 28 Aug 2025 20:38:23 -0400 Subject: [PATCH 4/4] clk: rp1: convert from round_rate() to determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney Link: https://lore.kernel.org/linux-clk/20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com/T/#mbb878a331cf0f8930257a356c1d9e2ab458e3efb Signed-off-by: Florian Fainelli --- drivers/clk/clk-rp1.c | 58 ++++++++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/drivers/clk/clk-rp1.c b/drivers/clk/clk-rp1.c index e8f264d7f34e..fd144755b879 100644 --- a/drivers/clk/clk-rp1.c +++ b/drivers/clk/clk-rp1.c @@ -532,13 +532,16 @@ static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw, return calc_rate; } -static long rp1_pll_core_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int rp1_pll_core_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { u32 fbdiv_int, fbdiv_frac; - return get_pll_core_divider(hw, rate, *parent_rate, - &fbdiv_int, &fbdiv_frac); + req->rate = get_pll_core_divider(hw, req->rate, req->best_parent_rate, + &fbdiv_int, + &fbdiv_frac); + + return 0; } static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate, @@ -616,18 +619,20 @@ static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw, return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2); } -static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int rp1_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_hw *clk_audio_hw = &clk_audio->hw; u32 div1, div2; - if (hw == clk_audio_hw && clk_audio->cached_rate == rate) - *parent_rate = clk_audio_core->cached_rate; + if (hw == clk_audio_hw && clk_audio->cached_rate == req->rate) + req->best_parent_rate = clk_audio_core->cached_rate; - get_pll_prim_dividers(rate, *parent_rate, &div1, &div2); + get_pll_prim_dividers(req->rate, req->best_parent_rate, &div1, &div2); - return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2); + req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, div1 * div2); + + return 0; } static int rp1_pll_ph_is_on(struct clk_hw *hw) @@ -677,13 +682,15 @@ static unsigned long rp1_pll_ph_recalc_rate(struct clk_hw *hw, return parent_rate / data->fixed_divider; } -static long rp1_pll_ph_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int rp1_pll_ph_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); const struct rp1_pll_ph_data *data = pll_ph->data; - return *parent_rate / data->fixed_divider; + req->rate = req->best_parent_rate / data->fixed_divider; + + return 0; } static int rp1_pll_divider_is_on(struct clk_hw *hw) @@ -760,11 +767,12 @@ static unsigned long rp1_pll_divider_recalc_rate(struct clk_hw *hw, return clk_divider_ops.recalc_rate(hw, parent_rate); } -static long rp1_pll_divider_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *parent_rate) +static int rp1_pll_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - return clk_divider_ops.round_rate(hw, rate, parent_rate); + req->rate = clk_divider_ops.determine_rate(hw, req); + + return 0; } static int rp1_clock_is_on(struct clk_hw *hw) @@ -1166,10 +1174,10 @@ static unsigned long rp1_varsrc_recalc_rate(struct clk_hw *hw, return clock->cached_rate; } -static long rp1_varsrc_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int rp1_varsrc_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - return rate; + return 0; } static const struct clk_ops rp1_pll_core_ops = { @@ -1178,13 +1186,13 @@ static const struct clk_ops rp1_pll_core_ops = { .unprepare = rp1_pll_core_off, .set_rate = rp1_pll_core_set_rate, .recalc_rate = rp1_pll_core_recalc_rate, - .round_rate = rp1_pll_core_round_rate, + .determine_rate = rp1_pll_core_determine_rate, }; static const struct clk_ops rp1_pll_ops = { .set_rate = rp1_pll_set_rate, .recalc_rate = rp1_pll_recalc_rate, - .round_rate = rp1_pll_round_rate, + .determine_rate = rp1_pll_determine_rate, }; static const struct clk_ops rp1_pll_ph_ops = { @@ -1192,7 +1200,7 @@ static const struct clk_ops rp1_pll_ph_ops = { .prepare = rp1_pll_ph_on, .unprepare = rp1_pll_ph_off, .recalc_rate = rp1_pll_ph_recalc_rate, - .round_rate = rp1_pll_ph_round_rate, + .determine_rate = rp1_pll_ph_determine_rate, }; static const struct clk_ops rp1_pll_divider_ops = { @@ -1201,7 +1209,7 @@ static const struct clk_ops rp1_pll_divider_ops = { .unprepare = rp1_pll_divider_off, .set_rate = rp1_pll_divider_set_rate, .recalc_rate = rp1_pll_divider_recalc_rate, - .round_rate = rp1_pll_divider_round_rate, + .determine_rate = rp1_pll_divider_determine_rate, }; static const struct clk_ops rp1_clk_ops = { @@ -1219,7 +1227,7 @@ static const struct clk_ops rp1_clk_ops = { static const struct clk_ops rp1_varsrc_ops = { .set_rate = rp1_varsrc_set_rate, .recalc_rate = rp1_varsrc_recalc_rate, - .round_rate = rp1_varsrc_round_rate, + .determine_rate = rp1_varsrc_determine_rate, }; static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman,