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cxl/pci: Update only the Port GPF timeout fields

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update_gpf_port_dvsec() rebuilds the phase control register from just
the timeout base and scale, so the rest of the register is cleared by
the write. The other bits are reserved today and nothing is lost, but
the full-register rewrite would clobber any field the spec defines
there later.

Read-modify-write the register and change only the two timeout
fields.

Fixes: a52b6a2c1c ("cxl/pci: Support Global Persistent Flush (GPF)")
Assisted-by: LLM
Signed-off-by: Guixin Liu <kanie@linux.alibaba.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20261008034619.28059-4-kanie@linux.alibaba.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
This commit is contained in:
Guixin Liu 2026-10-08 11:46:14 +08:00 committed by Dave Jiang
parent ec2e30a682
commit b5d14009bd
1 changed files with 2 additions and 2 deletions
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4
drivers/cxl/core/pci.c
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@ -861,8 +861,8 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
FIELD_GET(scale, ctrl) == GPF_TIMEOUT_SCALE_MAX)
return 0;
ctrl = FIELD_PREP(base, GPF_TIMEOUT_BASE_MAX);
ctrl |= FIELD_PREP(scale, GPF_TIMEOUT_SCALE_MAX);
FIELD_MODIFY(base, &ctrl, GPF_TIMEOUT_BASE_MAX);
FIELD_MODIFY(scale, &ctrl, GPF_TIMEOUT_SCALE_MAX);
rc = pci_write_config_word(pdev, dvsec + offset, ctrl);
if (rc) {