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drm/i915/cmtg: Set CMTG clock select

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Program the CMTG Clock Select register based on the transcoder used.

v2:
- Correct mask for PHY B. [Jani]
- Use REG_FIELD_PREP() for enable value. [Dibin]
- Extend cmtg clock select for xe3plpd. [Dibin]

v3:
- CMTG support removed for old platform.

v4:
- Optimize further with else-if. [Uma]
- Correct CMTG_CLK_SEL_B_MASK. [Uma]

v5:
- Add transcoder-port compatibility check. [Dibin]

Bspec: 69103
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Link: https://patch.msgid.link/20260615200339.885190-3-animesh.manna@intel.com
This commit is contained in:
Animesh Manna 2026-06-16 01:33:19 +05:30
parent 21ebf55d69
commit b5cbe1aefe
4 changed files with 36 additions and 0 deletions
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22
drivers/gpu/drm/i915/display/intel_cmtg.c
View File

@ -197,3 +197,25 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
return false;
}
void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 clk_sel_clr = 0;
u32 clk_sel_set = 0;
if (!intel_cmtg_is_allowed(crtc_state))
return;
if (cpu_transcoder == TRANSCODER_A) {
clk_sel_clr = CMTG_CLK_SEL_A_MASK;
clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
} else if (cpu_transcoder == TRANSCODER_B) {
clk_sel_clr = CMTG_CLK_SEL_B_MASK;
clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
}
if (clk_sel_set)
intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
}

1
drivers/gpu/drm/i915/display/intel_cmtg.h
View File

@ -11,6 +11,7 @@
struct intel_display;
struct intel_crtc_state;
void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
void intel_cmtg_sanitize(struct intel_display *display);
bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);

2
drivers/gpu/drm/i915/display/intel_cmtg_regs.h
View File

@ -10,8 +10,10 @@
#define CMTG_CLK_SEL _MMIO(0x46160)
#define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29)
#define CMTG_CLK_SELECT_PHYA_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
#define CMTG_CLK_SEL_A_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
#define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13)
#define CMTG_CLK_SELECT_PHYB_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
#define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
#define TRANS_CMTG_CTL_A _MMIO(0x6fa88)

11
drivers/gpu/drm/i915/display/intel_cx0_phy.c
View File

@ -9,6 +9,7 @@
#include <drm/drm_print.h>
#include "intel_alpm.h"
#include "intel_cmtg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
#include "intel_display_regs.h"
@ -3418,10 +3419,20 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
if (intel_tc_port_in_tbt_alt_mode(dig_port))
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
/*
* CMTG can be enabled only when the transcoder and port are compatible
* (transcoder A with port A, transcoder B with port B).
*/
if (HAS_LT_PHY(display) &&
((crtc_state->cpu_transcoder == TRANSCODER_A && encoder->port == PORT_A) ||
(crtc_state->cpu_transcoder == TRANSCODER_B && encoder->port == PORT_B)))
intel_cmtg_set_clk_select(crtc_state);
}
/*