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https://github.com/torvalds/linux.git
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Microchip clock updates for v6.19
This update includes: - PolarFire SoC clock driver updates to use regmaps instead of iomem addresses; with it, the reset control driver support for non-auxiliary bus probing was included as it now depends on the regmap registered by the clock controller driver - a cleanup patch for the LAN966X driver -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCaSC8JAAKCRCejrg/N2X7 /VJKAQCIayI8cmVmk9G6rdNhwk/h0BxPticIp5kPcROOy5MffgEAolzmLq7bitkY /AkEzmYybLvD75T/mPpB2l+HSXoVIAM= =oIV5 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmksnKsUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSX94g//WgI47agitjb8GlCz+xuH3wE1uA/n dD9FgrfkpCVetaz8avQ+1ZzfEd5Rl9kt93sNjuB62OknDtq0MSdE7fsiZ5freC+j qTGFLuFuKKsdOJbcJFKfmYFMCfDwU9AEd6bLnOCA+2we6y5s6pk1YNYZy52zzpXX Lto3sXnwtBzYTMJ0G1nTD+BiJGjOwmC9+xZ6Ndpp4NqO5bd+1F7tZACJUQ/53lwF QVctv//5NqxQ+ZrCog7FyqY2SJIN0vJ57M6RCMAqdAyihnEh8r/U4H1YdB7tjYSd csl+vTdFSoGCdaxMMEAsUFqlQ+1PwpIg+LzCONCaVtSoN+jW6VgTfPnM1sbNpQjr CpC0FCuv58aM+vVsuIE10hUdu6ZRR/cJpwZk2u1xeCeuT1I1sqXfNfMd2P+hgrEP xoBZavClb3CksMX1GemK46aCVCpG8skJ7+QHTSG3pvkyS4iYgTOQyqXPt7mPFvD7 M3nWer62YS+52+9ybC8vanRrE5/RLNxOMgUl0MV5pXy8EwLPmcp9FVAv0bl+RZHv Hqb4zGmngFmgQ3v9BOTZsvbfA7/3mG0KtYm2+MYURueObNezKDM64hbt8OTKTYYt nTAFCp+RCo7FwP2gWpvApaWhDr52rC+1BVwVb0/jSoqlSn7MNQiPbrUtQw6e0hrx pE0yo9s+g2ik3mo= =B8Ia -----END PGP SIGNATURE----- Merge tag 'clk-microchip-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clk driver updates from Claudiu Beznea: - PolarFire SoC clock driver updates to use regmaps instead of iomem addresses; with it, the reset control driver support for non-auxiliary bus probing was included as it now depends on the regmap registered by the clock controller driver - A cleanup patch for the LAN966X clk driver * tag 'clk-microchip-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: reset: mpfs: add non-auxiliary bus probing clk: lan966x: remove unused dt-bindings include clk: microchip: mpfs: use regmap for clocks dt-bindings: clk: microchip: mpfs: remove first reg region
This commit is contained in:
Stephen Boyd
commit
b5b9e93bbf
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@ -22,16 +22,23 @@ properties:
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const: microchip,mpfs-clkcfg
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reg:
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items:
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- description: |
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clock config registers:
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These registers contain enable, reset & divider tables for the, cpu,
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axi, ahb and rtc/mtimer reference clocks as well as enable and reset
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for the peripheral clocks.
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- description: |
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mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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oneOf:
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- items:
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- description: |
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clock config registers:
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These registers contain enable, reset & divider tables for the, cpu,
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axi, ahb and rtc/mtimer reference clocks as well as enable and reset
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for the peripheral clocks.
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- description: |
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mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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deprecated: true
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- items:
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- description: |
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mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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clocks:
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maxItems: 1
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@ -69,11 +76,12 @@ examples:
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- |
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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clkcfg: clock-controller@20002000 {
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#address-cells = <1>;
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#size-cells = <1>;
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clkcfg: clock-controller@3E001000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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reg = <0x3E001000 0x1000>;
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clocks = <&ref>;
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#clock-cells = <1>;
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};
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@ -16,8 +16,6 @@
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/microchip,lan966x.h>
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#define GCK_ENA BIT(0)
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#define GCK_SRC_SEL GENMASK(9, 8)
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#define GCK_PRESCALER GENMASK(23, 16)
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@ -7,6 +7,8 @@ config MCHP_CLK_MPFS
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bool "Clk driver for PolarFire SoC"
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depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
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default ARCH_MICROCHIP_POLARFIRE
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depends on MFD_SYSCON
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select AUXILIARY_BUS
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select REGMAP_MMIO
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help
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Supports Clock Configuration for PolarFire SoC
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@ -4,10 +4,13 @@
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*
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* Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
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*/
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#include <linux/cleanup.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
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#include <soc/microchip/mpfs.h>
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@ -30,6 +33,14 @@
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#define MSSPLL_POSTDIV_WIDTH 0x07u
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#define MSSPLL_FIXED_DIV 4u
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static const struct regmap_config mpfs_clk_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.max_register = REG_SUBBLK_RESET_CR,
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};
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/*
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* This clock ID is defined here, rather than the binding headers, as it is an
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* internal clock only, and therefore has no consumers in other peripheral
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@ -39,6 +50,7 @@
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struct mpfs_clock_data {
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struct device *dev;
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struct regmap *regmap;
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void __iomem *base;
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void __iomem *msspll_base;
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struct clk_hw_onecell_data hw_data;
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@ -67,21 +79,39 @@ struct mpfs_msspll_out_hw_clock {
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#define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw)
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struct mpfs_cfg_clock {
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struct regmap *map;
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const struct clk_div_table *table;
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u8 map_offset;
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u8 shift;
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u8 width;
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u8 flags;
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};
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struct mpfs_cfg_hw_clock {
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struct clk_divider cfg;
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struct clk_init_data init;
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struct clk_hw hw;
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struct mpfs_cfg_clock cfg;
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unsigned int id;
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u32 reg_offset;
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};
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#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
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struct mpfs_periph_clock {
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struct regmap *map;
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u8 map_offset;
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u8 shift;
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};
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struct mpfs_periph_hw_clock {
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struct clk_gate periph;
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struct clk_hw hw;
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struct mpfs_periph_clock periph;
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unsigned int id;
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};
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#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)
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/*
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* mpfs_clk_lock prevents anything else from writing to the
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* mpfs clk block while a software locked register is being written.
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* Protects MSSPLL outputs, since there's two to a register
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*/
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static DEFINE_SPINLOCK(mpfs_clk_lock);
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@ -219,16 +249,61 @@ static int mpfs_clk_register_msspll_outs(struct device *dev,
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/*
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* "CFG" clocks
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*/
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static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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u32 val;
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#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
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.id = _id, \
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.cfg.shift = _shift, \
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.cfg.width = _width, \
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.cfg.table = _table, \
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.reg_offset = _offset, \
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.cfg.flags = _flags, \
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.cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
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.cfg.lock = &mpfs_clk_lock, \
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regmap_read(cfg->map, cfg->map_offset, &val);
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val >>= cfg->shift;
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val &= clk_div_mask(cfg->width);
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return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
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}
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static int mpfs_cfg_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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return divider_determine_rate(hw, req, cfg->table, cfg->width, 0);
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}
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static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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int divider_setting;
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u32 val;
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u32 mask;
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divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0);
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if (divider_setting < 0)
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return divider_setting;
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mask = clk_div_mask(cfg->width) << cfg->shift;
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val = divider_setting << cfg->shift;
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regmap_update_bits(cfg->map, cfg->map_offset, val, mask);
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return 0;
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}
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static const struct clk_ops mpfs_clk_cfg_ops = {
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.recalc_rate = mpfs_cfg_clk_recalc_rate,
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.determine_rate = mpfs_cfg_clk_determine_rate,
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.set_rate = mpfs_cfg_clk_set_rate,
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};
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#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
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.id = _id, \
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.cfg.shift = _shift, \
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.cfg.width = _width, \
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.cfg.table = _table, \
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.cfg.map_offset = _offset, \
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.cfg.flags = _flags, \
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.hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \
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}
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#define CLK_CPU_OFFSET 0u
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@ -248,10 +323,10 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
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.cfg.shift = 0,
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.cfg.width = 12,
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.cfg.table = mpfs_div_rtcref_table,
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.reg_offset = REG_RTC_CLOCK_CR,
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.cfg.map_offset = REG_RTC_CLOCK_CR,
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.cfg.flags = CLK_DIVIDER_ONE_BASED,
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.cfg.hw.init =
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CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
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.hw.init =
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CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0),
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}
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};
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@ -264,14 +339,14 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *
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for (i = 0; i < num_clks; i++) {
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struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
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cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
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ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);
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cfg_hw->cfg.map = data->regmap;
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ret = devm_clk_hw_register(dev, &cfg_hw->hw);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
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cfg_hw->id);
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id = cfg_hw->id;
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data->hw_data.hws[id] = &cfg_hw->cfg.hw;
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data->hw_data.hws[id] = &cfg_hw->hw;
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}
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return 0;
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@ -281,15 +356,50 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *
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* peripheral clocks - devices connected to axi or ahb buses.
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*/
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#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
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.id = _id, \
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.periph.bit_idx = _shift, \
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.periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
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_flags), \
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.periph.lock = &mpfs_clk_lock, \
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static int mpfs_periph_clk_enable(struct clk_hw *hw)
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{
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struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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struct mpfs_periph_clock *periph = &periph_hw->periph;
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regmap_update_bits(periph->map, periph->map_offset,
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BIT(periph->shift), BIT(periph->shift));
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return 0;
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}
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#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)
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static void mpfs_periph_clk_disable(struct clk_hw *hw)
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{
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struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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struct mpfs_periph_clock *periph = &periph_hw->periph;
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regmap_update_bits(periph->map, periph->map_offset, BIT(periph->shift), 0);
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}
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static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)
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{
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struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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struct mpfs_periph_clock *periph = &periph_hw->periph;
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u32 val;
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regmap_read(periph->map, periph->map_offset, &val);
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return !!(val & BIT(periph->shift));
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}
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static const struct clk_ops mpfs_periph_clk_ops = {
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.enable = mpfs_periph_clk_enable,
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.disable = mpfs_periph_clk_disable,
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.is_enabled = mpfs_periph_clk_is_enabled,
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};
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#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
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.id = _id, \
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.periph.map_offset = REG_SUBBLK_CLOCK_CR, \
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.periph.shift = _shift, \
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.hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, _flags), \
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}
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#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw)
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/*
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* Critical clocks:
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@ -346,19 +456,55 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c
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for (i = 0; i < num_clks; i++) {
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struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
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periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
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ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);
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periph_hw->periph.map = data->regmap;
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ret = devm_clk_hw_register(dev, &periph_hw->hw);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
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periph_hw->id);
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id = periph_hws[i].id;
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data->hw_data.hws[id] = &periph_hw->periph.hw;
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data->hw_data.hws[id] = &periph_hw->hw;
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}
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return 0;
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}
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static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data,
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struct platform_device *pdev)
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{
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clk_data->regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-mss-top-sysreg");
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if (IS_ERR(clk_data->regmap))
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return PTR_ERR(clk_data->regmap);
|
||||
|
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clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 0);
|
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if (IS_ERR(clk_data->msspll_base))
|
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return PTR_ERR(clk_data->msspll_base);
|
||||
|
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return 0;
|
||||
}
|
||||
|
||||
static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_data,
|
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struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
dev_warn(&pdev->dev, "falling back to old devicetree format");
|
||||
|
||||
clk_data->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(clk_data->base))
|
||||
return PTR_ERR(clk_data->base);
|
||||
|
||||
clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(clk_data->msspll_base))
|
||||
return PTR_ERR(clk_data->msspll_base);
|
||||
|
||||
clk_data->regmap = devm_regmap_init_mmio(dev, clk_data->base, &mpfs_clk_regmap_config);
|
||||
if (IS_ERR(clk_data->regmap))
|
||||
return PTR_ERR(clk_data->regmap);
|
||||
|
||||
return mpfs_reset_controller_register(dev, clk_data->regmap);
|
||||
}
|
||||
|
||||
static int mpfs_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -374,13 +520,12 @@ static int mpfs_clk_probe(struct platform_device *pdev)
|
|||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
clk_data->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(clk_data->base))
|
||||
return PTR_ERR(clk_data->base);
|
||||
|
||||
clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(clk_data->msspll_base))
|
||||
return PTR_ERR(clk_data->msspll_base);
|
||||
ret = mpfs_clk_syscon_probe(clk_data, pdev);
|
||||
if (ret) {
|
||||
ret = mpfs_clk_old_format_probe(clk_data, pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
clk_data->hw_data.num = num_clks;
|
||||
clk_data->dev = dev;
|
||||
|
|
@ -406,11 +551,7 @@ static int mpfs_clk_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id mpfs_clk_of_match_table[] = {
|
||||
|
|
|
|||
|
|
@ -200,6 +200,7 @@ config RESET_PISTACHIO
|
|||
config RESET_POLARFIRE_SOC
|
||||
bool "Microchip PolarFire SoC (MPFS) Reset Driver"
|
||||
depends on MCHP_CLK_MPFS
|
||||
depends on MFD_SYSCON
|
||||
select AUXILIARY_BUS
|
||||
default MCHP_CLK_MPFS
|
||||
help
|
||||
|
|
|
|||
|
|
@ -9,11 +9,13 @@
|
|||
#include <linux/auxiliary_bus.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
#include <dt-bindings/clock/microchip,mpfs-clock.h>
|
||||
#include <soc/microchip/mpfs.h>
|
||||
|
||||
|
|
@ -27,11 +29,10 @@
|
|||
#define MPFS_SLEEP_MIN_US 100
|
||||
#define MPFS_SLEEP_MAX_US 200
|
||||
|
||||
/* block concurrent access to the soft reset register */
|
||||
static DEFINE_SPINLOCK(mpfs_reset_lock);
|
||||
#define REG_SUBBLK_RESET_CR 0x88u
|
||||
|
||||
struct mpfs_reset {
|
||||
void __iomem *base;
|
||||
struct regmap *regmap;
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
|
||||
|
|
@ -46,41 +47,25 @@ static inline struct mpfs_reset *to_mpfs_reset(struct reset_controller_dev *rcde
|
|||
static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&mpfs_reset_lock, flags);
|
||||
return regmap_set_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id));
|
||||
|
||||
reg = readl(rst->base);
|
||||
reg |= BIT(id);
|
||||
writel(reg, rst->base);
|
||||
|
||||
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&mpfs_reset_lock, flags);
|
||||
return regmap_clear_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id));
|
||||
|
||||
reg = readl(rst->base);
|
||||
reg &= ~BIT(id);
|
||||
writel(reg, rst->base);
|
||||
|
||||
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
|
||||
u32 reg = readl(rst->base);
|
||||
u32 reg;
|
||||
|
||||
regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®);
|
||||
|
||||
/*
|
||||
* It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
|
||||
|
|
@ -130,23 +115,58 @@ static int mpfs_reset_xlate(struct reset_controller_dev *rcdev,
|
|||
return index - MPFS_PERIPH_OFFSET;
|
||||
}
|
||||
|
||||
static int mpfs_reset_probe(struct auxiliary_device *adev,
|
||||
const struct auxiliary_device_id *id)
|
||||
static int mpfs_reset_mfd_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &adev->dev;
|
||||
struct reset_controller_dev *rcdev;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mpfs_reset *rst;
|
||||
|
||||
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
|
||||
if (!rst)
|
||||
return -ENOMEM;
|
||||
|
||||
rst->base = (void __iomem *)adev->dev.platform_data;
|
||||
rcdev = &rst->rcdev;
|
||||
rcdev->dev = dev;
|
||||
rcdev->ops = &mpfs_reset_ops;
|
||||
|
||||
rcdev->of_node = pdev->dev.parent->of_node;
|
||||
rcdev->of_reset_n_cells = 1;
|
||||
rcdev->of_xlate = mpfs_reset_xlate;
|
||||
rcdev->nr_resets = MPFS_NUM_RESETS;
|
||||
|
||||
rst->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
|
||||
if (IS_ERR(rst->regmap))
|
||||
return dev_err_probe(dev, PTR_ERR(rst->regmap),
|
||||
"Failed to find syscon regmap\n");
|
||||
|
||||
return devm_reset_controller_register(dev, rcdev);
|
||||
}
|
||||
|
||||
static struct platform_driver mpfs_reset_mfd_driver = {
|
||||
.probe = mpfs_reset_mfd_probe,
|
||||
.driver = {
|
||||
.name = "mpfs-reset",
|
||||
},
|
||||
};
|
||||
module_platform_driver(mpfs_reset_mfd_driver);
|
||||
|
||||
static int mpfs_reset_adev_probe(struct auxiliary_device *adev,
|
||||
const struct auxiliary_device_id *id)
|
||||
{
|
||||
struct reset_controller_dev *rcdev;
|
||||
struct device *dev = &adev->dev;
|
||||
struct mpfs_reset *rst;
|
||||
|
||||
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
|
||||
if (!rst)
|
||||
return -ENOMEM;
|
||||
|
||||
rst->regmap = (struct regmap *)adev->dev.platform_data;
|
||||
|
||||
rcdev = &rst->rcdev;
|
||||
rcdev->dev = dev;
|
||||
rcdev->dev->parent = dev->parent;
|
||||
rcdev->ops = &mpfs_reset_ops;
|
||||
|
||||
rcdev->of_node = dev->parent->of_node;
|
||||
rcdev->of_reset_n_cells = 1;
|
||||
rcdev->of_xlate = mpfs_reset_xlate;
|
||||
|
|
@ -155,12 +175,11 @@ static int mpfs_reset_probe(struct auxiliary_device *adev,
|
|||
return devm_reset_controller_register(dev, rcdev);
|
||||
}
|
||||
|
||||
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base)
|
||||
int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *map)
|
||||
{
|
||||
struct auxiliary_device *adev;
|
||||
|
||||
adev = devm_auxiliary_device_create(clk_dev, "reset-mpfs",
|
||||
(__force void *)base);
|
||||
adev = devm_auxiliary_device_create(clk_dev, "reset-mpfs", (void *)map);
|
||||
if (!adev)
|
||||
return -ENODEV;
|
||||
|
||||
|
|
@ -176,12 +195,12 @@ static const struct auxiliary_device_id mpfs_reset_ids[] = {
|
|||
};
|
||||
MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);
|
||||
|
||||
static struct auxiliary_driver mpfs_reset_driver = {
|
||||
.probe = mpfs_reset_probe,
|
||||
static struct auxiliary_driver mpfs_reset_aux_driver = {
|
||||
.probe = mpfs_reset_adev_probe,
|
||||
.id_table = mpfs_reset_ids,
|
||||
};
|
||||
|
||||
module_auxiliary_driver(mpfs_reset_driver);
|
||||
module_auxiliary_driver(mpfs_reset_aux_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
|
||||
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
|
||||
#include <linux/types.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
struct mpfs_sys_controller;
|
||||
|
||||
|
|
@ -44,7 +45,7 @@ struct mtd_info *mpfs_sys_controller_get_flash(struct mpfs_sys_controller *mpfs_
|
|||
|
||||
#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
|
||||
#if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC)
|
||||
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base);
|
||||
int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *map);
|
||||
#else
|
||||
static inline int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base) { return 0; }
|
||||
#endif /* if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC) */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user