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video: rockchip: delete some useless file

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Change-Id: Idfe4cfcfdbf2957b78eb41d0ec6837b6479c49e4
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
This commit is contained in:
Huang Jiachai 2015-12-04 17:48:12 +08:00
parent 83ec27d53c
commit b58cbf93e0
13 changed files with 0 additions and 8487 deletions
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33
drivers/video/display/screen/Kconfig
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@ -1,33 +0,0 @@
choice
depends on FB_RK29
prompt "LCD Panel Select for rk2918 platform"
config LCD_RK29_NULL
bool "NULL"
config LCD_RK29_LG_LP097X02
bool "RGB LCD_LG_LP097X02 1024X768"
config LCD_RK29_HSD100PXN
bool "RGB Hannstar HSD100PXN(1024X768)"
config LCD_RK29_LS035Y8DX02A
bool "RGB LS035Y8DX02A(480X800)"
config LCD_RK29_LS035Y8DX04A
bool "RGB LS035Y8DX04A(480X800)"
config LCD_RK29_NT35510
bool "RGB lcd_nt35510"
config DEFAULT_OUT_HDMI
bool "HDMI for default panel"
depends on HDMI
---help---
if you want set HDMI for default panel, android UI size is HDMI default resolution.
config LCD_RK29_A050VL01
bool "RGB A050VL01"
endchoice

12
drivers/video/display/screen/Makefile
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obj-$(CONFIG_LCD_RK29_NULL) += lcd_null.o
obj-$(CONFIG_LCD_RK29_LG_LP097X02)+= lcd_LG_LP097X02.o
obj-$(CONFIG_LCD_RK29_LS035Y8DX02A) += lcd_ls035y8dx02a.o
obj-$(CONFIG_LCD_RK29_LS035Y8DX04A) += lcd_ls035y8dx04a.o
obj-$(CONFIG_LCD_RK29_HSD100PXN) += lcd_hsd100pxn.o
obj-$(CONFIG_LCD_RK29_NT35510) += lcd_nt35510.o
obj-$(CONFIG_LCD_RK29_A050VL01) += lcd_A050VL01.o

348
drivers/video/display/screen/lcd_A050VL01.c
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/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 23500000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
#define H_PW 2
#define H_BP 2
#define H_VD 480
#define H_FP 2
#define V_PW 2
#define V_BP 2
#define V_VD 800
#define V_FP 2
/* Other */
#define DCLK_POL 1
#define SWAP_RB 0
#define LCD_WIDTH 480 //need modify
#define LCD_HEIGHT 800
#if 1
#define RXD_PORT RK29_PIN2_PC7
#define TXD_PORT gLcd_info->txd_pin
#define CLK_PORT gLcd_info->clk_pin
#define CS_PORT gLcd_info->cs_pin
#define RESET_PORT RK29_PIN6_PC6
#define CS_OUT() gpio_direction_output(CS_PORT, 1)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 1)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#define RXD_IN() gpio_direction_input(RXD_PORT)
#define RXD_GET() gpio_get_value(RXD_PORT)
#endif
static struct rk29lcd_info *gLcd_info = NULL;
#define DRVDelayUs(i) udelay(i*4)
int init(void);
int standby(u8 enable);
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = init;
/*screen->init = NULL;*/
screen->standby = standby;
if(lcd_info)
gLcd_info = lcd_info;
}
//cannot need init,so set screen->init = null at rk29_fb.c file
#if 1
void spi_screenreg_command(u16 command)
{
u8 i,buff;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_SET();
DRVDelayUs(2);
buff = 0x20;
CS_CLR();
for(i = 0; i < 8; i++)
{
if(buff & (1<<(7-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
for(i = 0; i < 8; i++) //reg hight
{
if(command &(1<<(15-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
buff = 0x00;
CS_CLR();
for(i = 0; i < 8; i++)
{
if(buff & (1<<(7-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
for(i = 8; i < 16; i++) //reg low
{
if(command &(1<<(15-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
}
void spi_screenreg_command_data(u16 Addr, u16 Data)
{
u8 i,buff;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_SET();
DRVDelayUs(2);
buff = 0x20;
CS_CLR();
for(i = 0; i < 8; i++)
{
if(buff & (1<<(7-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
for(i = 0; i < 8; i++) //reg hight
{
if(Addr &(1<<(15-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
buff = 0x00;
CS_CLR();
for(i = 0; i < 8; i++)
{
if(buff & (1<<(7-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
for(i = 8; i < 16; i++) //reg low
{
if(Addr &(1<<(15-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
buff = 0x40;
CS_CLR();
for(i = 0; i < 8; i++)
{
if(buff & (1<<(7-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
for(i = 0; i < 8; i++) //data
{
if(Data &(1<<(7-i)))
TXD_SET();
else
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
}
int init(void)
{
if(gLcd_info)
gLcd_info->io_init();
#ifdef RESET_PORT
gpio_request(RESET_PORT, NULL);
gpio_direction_output(RESET_PORT, 0);
mdelay(2);
gpio_set_value(RESET_PORT, 1);
mdelay(10);
gpio_free(RESET_PORT);
#endif
spi_screenreg_command(0x1100);
spi_screenreg_command_data(0xC000,0x8a);
spi_screenreg_command_data(0xC002,0x8a);
spi_screenreg_command_data(0xC200,0x02);
spi_screenreg_command_data(0xC202,0x32);
spi_screenreg_command_data(0xC100,0x40);
spi_screenreg_command_data(0xC700,0x8b);
mdelay(200);
spi_screenreg_command(0x2900);
spi_screenreg_command(0x2C00);
if(gLcd_info)
gLcd_info->io_deinit();
return 0;
}
#endif
extern void rk29_lcd_spim_spin_lock(void);
extern void rk29_lcd_spim_spin_unlock(void);
int standby(u8 enable)
{
rk29_lcd_spim_spin_lock();
if(gLcd_info)
gLcd_info->io_init();
if(enable) {
#ifdef RESET_PORT
gpio_request(RESET_PORT, NULL);
gpio_direction_output(RESET_PORT, 0);
mdelay(2);
gpio_set_value(RESET_PORT, 1);
mdelay(10);
gpio_free(RESET_PORT);
#endif
spi_screenreg_command(0x2800);
spi_screenreg_command(0x1000);
} else {
init();
}
if(gLcd_info)
gLcd_info->io_deinit();
rk29_lcd_spim_spin_unlock();
return 0;
}

72
drivers/video/display/screen/lcd_LG_LP097X02.c
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@ -1,72 +0,0 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_D888_P666
#define OUT_CLK 100000000
#define LCDC_ACLK 500000000
/* Timing */
#define H_PW 320
#define H_BP 480
#define H_VD 1024
#define H_FP 260
#define V_PW 10
#define V_BP 6
#define V_VD 768
#define V_FP 16
#define LCD_WIDTH 196// 142 // 202
#define LCD_HEIGHT 147 //106// 152
/* Other */
#define DCLK_POL 1 //
#define SWAP_RB 0
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
}

308
drivers/video/display/screen/lcd_hsd100pxn.c
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@ -1,308 +0,0 @@
#include <linux/rk_fb.h>
#include <linux/delay.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "../../rockchip/hdmi/rk_hdmi.h"
/* Base */
#define OUT_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_D888_P666
#define OUT_CLK 65000000
#define LCDC_ACLK 300000000//312000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
#define H_PW 10
#define H_BP 100
#define H_VD 1024
#define H_FP 210
#define V_PW 10
#define V_BP 10
#define V_VD 768
#define V_FP 18
#define LCD_WIDTH 202
#define LCD_HEIGHT 152
/* Other */
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#ifdef CONFIG_ONE_LCDC_DUAL_OUTPUT_INF
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK 64512000
#define S_H_PW 114
#define S_H_BP 210
#define S_H_VD 1024
#define S_H_FP 0
#define S_V_PW 4
#define S_V_BP 10
#define S_V_VD 768
#define S_V_FP 0
#define S_H_ST 0
#define S_V_ST 23
//1920*1080*50
#define S1_OUT_CLK 53760000
#define S1_H_PW 114
#define S1_H_BP 210
#define S1_H_VD 1024
#define S1_H_FP 0
#define S1_V_PW 4
#define S1_V_BP 10
#define S1_V_VD 768
#define S1_V_FP 0
#define S1_H_ST 0
#define S1_V_ST 23
//1280*720*60
#define S2_OUT_CLK 64512000
#define S2_H_PW 114
#define S2_H_BP 210
#define S2_H_VD 1024
#define S2_H_FP 0
#define S2_V_PW 4
#define S2_V_BP 10
#define S2_V_VD 768
#define S2_V_FP 0
#define S2_H_ST 0
#define S2_V_ST 23
//1280*720*50
#define S3_OUT_CLK 53760000
#define S3_H_PW 114
#define S3_H_BP 210
#define S3_H_VD 1024
#define S3_H_FP 0
#define S3_V_PW 4
#define S3_V_BP 10
#define S3_V_VD 768
#define S3_V_FP 0
#define S3_H_ST 0
#define S3_V_ST 23
//720*576*50
#define S4_OUT_CLK 30000000
#define S4_H_PW 1
#define S4_H_BP 88
#define S4_H_VD 800
#define S4_H_FP 263
#define S4_V_PW 3
#define S4_V_BP 9
#define S4_V_VD 480
#define S4_V_FP 28
#define S4_H_ST 0
#define S4_V_ST 33
//720*480*60
#define S5_OUT_CLK 30000000
#define S5_H_PW 1
#define S5_H_BP 88
#define S5_H_VD 800
#define S5_H_FP 112
#define S5_V_PW 3
#define S5_V_BP 9
#define S5_V_VD 480
#define S5_V_FP 28
#define S5_H_ST 0
#define S5_V_ST 29
#define S_DCLK_POL 1
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
printk("%s>>>>>>>>mode:%d\n",__func__,hdmi_resolution);
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
#define set_scaler_info NULL
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
screen->hw_format = LVDS_FORMAT;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = HSYNC_POL;
screen->pin_vsync = VSYNC_POL;
screen->pin_den = DEN_POL;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_RG;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)
screen->sscreen_get = set_scaler_info;
screen->s_pixclock = OUT_CLK;
screen->s_hsync_len = H_PW;
screen->s_left_margin = H_BP;
screen->s_right_margin = H_FP;
screen->s_hsync_len = H_PW;
screen->s_upper_margin = V_BP;
screen->s_lower_margin = V_FP;
screen->s_vsync_len = V_PW;
screen->s_hsync_st = 0;
screen->s_vsync_st = 0;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

353
drivers/video/display/screen/lcd_ls035y8dx02a.c
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@ -1,353 +0,0 @@
/*
* Copyright (C) 2011 ROCKCHIP, Inc.
*
* author: hhb@rock-chips.com
* creat date: 2011-03-22
* route:drivers/video/display/screen/lcd_ls035y8dx02a.c - driver for rk29 phone sdk
* declaration: This program driver have been tested in rk29_phonesdk hardware platform at 2011.03.31.
* about migration: you need just 3 interface functions,such as lcd_init(void),lcd_standby(u8 enable),
* set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK (26*1000000) //***27 uint Hz
#define LCDC_ACLK 300000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 8 //16
#define H_BP 6//24
#define H_VD 480//320
#define H_FP 60//16
#define V_PW 2
#define V_BP 2
#define V_VD 800//480
#define V_FP 4
#define LCD_WIDTH 480 //need modify
#define LCD_HEIGHT 800
/* Other */
#define DCLK_POL 1 //0
#define SWAP_RB 0
static struct rk29lcd_info *gLcd_info = NULL;
int lcd_init(void);
int lcd_standby(u8 enable);
#define RXD_PORT RK29_PIN2_PC7
#define TXD_PORT gLcd_info->txd_pin
#define CLK_PORT gLcd_info->clk_pin
#define CS_PORT gLcd_info->cs_pin
#define RESET_PORT RK29_PIN6_PC6
#define CS_OUT() gpio_direction_output(CS_PORT, 1)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 1)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#define RXD_IN() gpio_direction_input(RXD_PORT)
#define RXD_GET() gpio_get_value(RXD_PORT)
#define DRVDelayUs(i) udelay(i*4)
u32 spi_screenreg_get(u32 Addr)
{
u32 i, data = 0;
u32 control_bit;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(30);
CS_CLR();
control_bit = 0x0000;
Addr = (control_bit | Addr);
printk("addr is 0x%x \n", Addr);
for(i = 0; i < 9; i++) //reg
{
if(Addr &(1<<(8-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
DRVDelayUs(2);
}
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(10);
CS_CLR();
for(i = 0; i < 9; i++)
{
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
if(RXD_GET())
{
data |= 1<<(8-i);
}
else
{
data &= ~(1<<(8-i));
}
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(30);
return data;
}
void spi_screenreg_set(u32 Addr, u32 Data0, u32 Data1)
{
u32 i;
u32 control_bit;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(30);
CS_CLR();
control_bit = 0x0000;
Addr = (control_bit | Addr);
//printk("addr is 0x%x \n", Addr);
for(i = 0; i < 9; i++) //reg
{
if(Addr &(1<<(8-i)))
TXD_SET();
else
TXD_CLR();
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
DRVDelayUs(2);
}
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(10);
if(0xffff == Data0){
return;
}
CS_CLR();
control_bit = 0x0100;
Data0 = (control_bit | Data0);
//printk("data0 is 0x%x \n", Data);
for(i = 0; i < 9; i++) //data
{
if(Data0 &(1<<(8-i)))
TXD_SET();
else
TXD_CLR();
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(10);
if(0xffff == Data1)
return;
CS_CLR();
control_bit = 0x0100;
Data1 = (control_bit | Data1);
//printk("data1 is 0x%x \n", Data);
for(i = 0; i < 9; i++) //data
{
if(Data1 &(1<<(8-i)))
TXD_SET();
else
TXD_CLR();
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(30);
}
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP; /*>2*/
screen->right_margin = H_FP; /*>2*/
screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4<PW+BP<15,
screen->upper_margin = V_BP; /*>2*/
screen->lower_margin = V_FP; /*>2*/
screen->vsync_len = V_PW; /*>6*/
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = lcd_init;
screen->standby = lcd_standby;
if(lcd_info)
gLcd_info = lcd_info;
}
int lcd_init(void)
{
volatile u32 data;
if(gLcd_info){
gLcd_info->io_init();
}
/* reset lcd to start init lcd by software if there is no hardware reset circuit for the lcd */
#ifdef RESET_PORT
gpio_request(RESET_PORT, NULL);
gpio_direction_output(RESET_PORT, 0);
mdelay(2);
gpio_set_value(RESET_PORT, 1);
mdelay(10);
gpio_free(RESET_PORT);
#endif
printk("lcd init...\n");
spi_screenreg_set(0x29, 0xffff, 0xffff); //display on
spi_screenreg_set(0x11, 0xffff, 0xffff); //sleep out
mdelay(150);
spi_screenreg_set(0x36, 0x0000, 0xffff); //set address mode
while(0) //this code is not used here
{
data = spi_screenreg_get(0x0a);
printk("------------liuylcd init reg 0x0a=0x%x \n", spi_screenreg_get(0x0a));
data = spi_screenreg_get(0x0b);
printk("------------liuylcd init reg 0x0b=0x%x \n", spi_screenreg_get(0x0b));
data = spi_screenreg_get(0x0c);
printk("------------liuylcd init reg 0x0c=0x%x \n", spi_screenreg_get(0x0c));
data = spi_screenreg_get(0x0d);
printk("------------liuylcd init reg 0x0d=0x%x \n", spi_screenreg_get(0x0d));
data = spi_screenreg_get(0x0f);
printk("------------liuylcd init reg 0x0f=0x%x \n", spi_screenreg_get(0x0f));
}
spi_screenreg_set(0x3a, 0x0070, 0xffff); //set pixel format
spi_screenreg_set(0xb0, 0x0000, 0xffff); //enable command acess
spi_screenreg_set(0xb8, 0x0001, 0xffff); //BLC setting
spi_screenreg_set(0xb9, 0x0001, 0x00ff); //LED PWM
spi_screenreg_set(0xb0, 0x0003, 0xffff); //disable command acess
if(gLcd_info)
gLcd_info->io_deinit();
return 0;
}
extern void rk29_lcd_spim_spin_lock(void);
extern void rk29_lcd_spim_spin_unlock(void);
int lcd_standby(u8 enable) //***enable =1 means suspend, 0 means resume
{
rk29_lcd_spim_spin_lock();
if(gLcd_info)
gLcd_info->io_init();
if(enable) {
//printk("lcd suspend\n");
spi_screenreg_set(0x10, 0xffff, 0xffff);
mdelay(120);
spi_screenreg_set(0x28, 0xffff, 0xffff);
} else {
//printk("lcd resume\n");
spi_screenreg_set(0x29, 0xffff, 0xffff);
spi_screenreg_set(0x11, 0xffff, 0xffff);
mdelay(130);
spi_screenreg_set(0x36, 0x0000, 0xffff); //set address mode
spi_screenreg_set(0x3a, 0x0070, 0xffff); //set pixel format
spi_screenreg_set(0xb0, 0x0000, 0xffff); //enable command acess
spi_screenreg_set(0xb8, 0x0001, 0xffff); //BLC setting
spi_screenreg_set(0xb9, 0x0001, 0x00ff); //LED PWM
spi_screenreg_set(0xb0, 0x0003, 0xffff); //disable command acess
}
if(gLcd_info)
gLcd_info->io_deinit();
rk29_lcd_spim_spin_unlock();
return 0;
}

347
drivers/video/display/screen/lcd_ls035y8dx04a.c
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@ -1,347 +0,0 @@
/*
* Copyright (C) 2011 ROCKCHIP, Inc.
*
* author: hhb@rock-chips.com
* creat date: 2011-03-22
* route:drivers/video/display/screen/lcd_ls035y8dx02a.c - driver for rk29 phone sdk
* declaration: This program driver have been tested in rk29_phonesdk hardware platform at 2011.03.31.
* about migration: you need just 3 interface functions,such as lcd_init(void),lcd_standby(u8 enable),
* set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK (26*1000000) //***27 uint Hz
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 8 //16
#define H_BP 6//24
#define H_VD 480//320
#define H_FP 60//16
#define V_PW 2
#define V_BP 2
#define V_VD 800//480
#define V_FP 4
#define LCD_WIDTH 46 //need modify
#define LCD_HEIGHT 76
/* Other */
#define DCLK_POL 1 //0
#define SWAP_RB 0
static struct rk29lcd_info *gLcd_info = NULL;
int lcd_init(void);
int lcd_standby(u8 enable);
#define RXD_PORT RK29_PIN2_PC7
#define TXD_PORT gLcd_info->txd_pin
#define CLK_PORT gLcd_info->clk_pin
#define CS_PORT gLcd_info->cs_pin
#define RESET_PORT RK29_PIN6_PC6
#define CS_OUT() gpio_direction_output(CS_PORT, 1)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 1)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#define RXD_IN() gpio_direction_input(RXD_PORT)
#define RXD_GET() gpio_get_value(RXD_PORT)
#define DRVDelayUs(i) udelay(i*4)
u32 spi_screenreg_get(u32 Addr)
{
u32 i, data = 0;
u32 control_bit;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(30);
CS_CLR();
control_bit = 0x0000;
Addr = (control_bit | Addr);
printk("addr is 0x%x \n", Addr);
for(i = 0; i < 9; i++) //reg
{
if(Addr &(1<<(8-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
DRVDelayUs(2);
}
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(10);
CS_CLR();
for(i = 0; i < 9; i++)
{
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
if(RXD_GET())
{
data |= 1<<(8-i);
}
else
{
data &= ~(1<<(8-i));
}
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(30);
return data;
}
void spi_screenreg_set(u32 Addr, u32 Data0, u32 Data1)
{
u32 i;
u32 control_bit;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(30);
CS_CLR();
control_bit = 0x0000;
Addr = (control_bit | Addr);
//printk("addr is 0x%x \n", Addr);
for(i = 0; i < 9; i++) //reg
{
if(Addr &(1<<(8-i)))
TXD_SET();
else
TXD_CLR();
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
DRVDelayUs(2);
}
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(10);
if(0xffff == Data0){
return;
}
CS_CLR();
control_bit = 0x0100;
Data0 = (control_bit | Data0);
//printk("data0 is 0x%x \n", Data);
for(i = 0; i < 9; i++) //data
{
if(Data0 &(1<<(8-i)))
TXD_SET();
else
TXD_CLR();
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(10);
if(0xffff == Data1)
return;
CS_CLR();
control_bit = 0x0100;
Data1 = (control_bit | Data1);
//printk("data1 is 0x%x \n", Data);
for(i = 0; i < 9; i++) //data
{
if(Data1 &(1<<(8-i)))
TXD_SET();
else
TXD_CLR();
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(30);
}
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP; /*>2*/
screen->right_margin = H_FP; /*>2*/
screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4<PW+BP<15,
screen->upper_margin = V_BP; /*>2*/
screen->lower_margin = V_FP; /*>2*/
screen->vsync_len = V_PW; /*>6*/
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = lcd_init;
screen->standby = lcd_standby;
if(lcd_info)
gLcd_info = lcd_info;
}
int lcd_init(void)
{
volatile u32 data;
if(gLcd_info){
gLcd_info->io_init();
}
/* reset lcd to start init lcd by software if there is no hardware reset circuit for the lcd */
#ifdef RESET_PORT
gpio_request(RESET_PORT, NULL);
gpio_direction_output(RESET_PORT, 0);
mdelay(2);
gpio_set_value(RESET_PORT, 1);
mdelay(10);
gpio_free(RESET_PORT);
#endif
printk("lcd init...\n");
spi_screenreg_set(0x29, 0xffff, 0xffff); //display on
spi_screenreg_set(0x11, 0xffff, 0xffff); //sleep out
mdelay(150);
spi_screenreg_set(0x36, 0x0000, 0xffff); //set address mode
while(0) //this code is not used here
{
data = spi_screenreg_get(0x0a);
printk("------------liuylcd init reg 0x0a=0x%x \n", spi_screenreg_get(0x0a));
data = spi_screenreg_get(0x0b);
printk("------------liuylcd init reg 0x0b=0x%x \n", spi_screenreg_get(0x0b));
data = spi_screenreg_get(0x0c);
printk("------------liuylcd init reg 0x0c=0x%x \n", spi_screenreg_get(0x0c));
data = spi_screenreg_get(0x0d);
printk("------------liuylcd init reg 0x0d=0x%x \n", spi_screenreg_get(0x0d));
data = spi_screenreg_get(0x0f);
printk("------------liuylcd init reg 0x0f=0x%x \n", spi_screenreg_get(0x0f));
}
spi_screenreg_set(0x3a, 0x0070, 0xffff); //set pixel format
spi_screenreg_set(0xb0, 0x0000, 0xffff); //enable command acess
spi_screenreg_set(0xb8, 0x0000, 0xffff); //BLC setting
spi_screenreg_set(0xb9, 0x0001, 0x00ff); //LED PWM
//spi_screenreg_set(0xb0, 0x0003, 0xffff); //disable command acess
if(gLcd_info)
gLcd_info->io_deinit();
return 0;
}
extern void rk29_lcd_spim_spin_lock(void);
extern void rk29_lcd_spim_spin_unlock(void);
int lcd_standby(u8 enable) //***enable =1 means suspend, 0 means resume
{
rk29_lcd_spim_spin_lock();
if(gLcd_info)
gLcd_info->io_init();
printk("lcd standby\n");
if(enable) {
printk("lcd standby...enable =1 means suspend\n");
spi_screenreg_set(0x10, 0xffff, 0xffff);
mdelay(120);
spi_screenreg_set(0x28, 0xffff, 0xffff);
} else {
printk("lcd standby...0 means resume\n");
spi_screenreg_set(0x29, 0xffff, 0xffff);
spi_screenreg_set(0x11, 0xffff, 0xffff);
//mdelay(150);
}
if(gLcd_info)
gLcd_info->io_deinit();
rk29_lcd_spim_spin_unlock();
return 0;
}

1633
drivers/video/display/screen/lcd_nt35510.c
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File diff suppressed because it is too large Load Diff

13
drivers/video/display/screen/lcd_null.c
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@ -1,13 +0,0 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <linux/rk_screen.h>
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info)
{
memset(screen, 0, sizeof(struct rk29fb_screen));
screen->face = OUT_P666;
}

1
drivers/video/display/screen/screen.h
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@ -1 +0,0 @@
/* empty */

1187
drivers/video/fb.uu
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File diff suppressed because it is too large Load Diff

3713
drivers/video/rk29_fb.c
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File diff suppressed because it is too large Load Diff

467
drivers/video/rk29_fb.h
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@ -1,467 +0,0 @@
/* drivers/video/rk29_fb.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_RK29_FB_H
#define __ARCH_ARM_MACH_RK29_FB_H
/********************************************************************
** 宏定义 *
********************************************************************/
/* 输往屏的数据格式 */
#define OUT_P888 0
#define OUT_P666 1 //666的屏, 接DATA0-17
#define OUT_P565 2 //565的屏, 接DATA0-15
#define OUT_S888x 4
#define OUT_CCIR656 6
#define OUT_S888 8
#define OUT_S888DUMY 12
#define OUT_P16BPP4 24 //模拟方式,控制器并不支持
#define OUT_D888_P666 0x21 //666的屏, 接DATA2-7, DATA10-15, DATA18-23
#define OUT_D888_P565 0x22 //565的屏, 接DATA3-7, DATA10-15, DATA19-23
/* SYS_CONFIG */
#define m_W2_FORMAT (3<<0)
#define m_W1_FORMAT (1<<2)
#define m_W0_FORMAT (7<<3)
#define m_W0_CBR_DEFLICK_EN (1<<6)
#define m_W0_YRGB_DEFLICK_EN (1<<7)
#define m_INTERIACE_EN (1<<8)
#define m_W2_ENABLE (1<<9)
#define m_W1_ENABLE (1<<10)
#define m_W0_ENABLE (1<<11)
#define m_HWC_ENABLE (1<<12)
#define m_HWC_RELOAD_EN (1<<13)
#define m_W2_INTERLACE_READ (1<<14)
#define m_W1_INTERLACE_READ (1<<15)
#define m_W0_INTERLACE_READ (1<<16)
#define m_STANDBY (1<<17)
#define m_HWC_BURST (3<<18)
#define m_W2_BURST (3<<20)
#define m_W1_BURST (3<<22)
#define m_W0_BURST (3<<24)
#define m_W2_LUT_CTL (1<<26)
#define m_DSIP_LUT_CTL (1<<27)
#define m_HWC_REVERSED_COLOR (1<<28)
#define m_W1_AXI_OUTSTANDING2 (1<<29)
#define m_W0_AXI_OUTSTANDING2 (1<<30)
#define v_W2_FORMAT(x) (((x)&3)<<0)
#define v_W1_FORMAT(x) (((x)&1)<<2)
#define v_W0_FORMAT(x) (((x)&7)<<3)
#define v_W0_CBR_DEFLICK_EN(x) (((x)&1)<<6)
#define v_W0_YRGB_DEFLICK_EN(x) (((x)&1)<<7)
#define v_INTERIACE_EN(x) (((x)&1)<<8)
#define v_W2_ENABLE(x) (((x)&)1<<9)
#define v_W1_ENABLE(x) (((x)&1)<<10)
#define v_W0_ENABLE(x) (((x)&1)<<11)
#define v_HWC_ENABLE(x) (((x)&1)<<12)
#define v_HWC_RELOAD_EN(x) (((x)&1)<<13)
#define v_W2_INTERLACE_READ(x) (((x)&1)<<14)
#define v_W1_INTERLACE_READ(x) (((x)&1)<<15)
#define v_W0_INTERLACE_READ(x) (((x)&1)<<16)
#define v_STANDBY(x) (((x)&1)<<17)
#define v_HWC_BURST(x) (((x)&3)<<18)
#define v_W2_BURST(x) (((x)&3)<<20)
#define v_W1_BURST(x) (((x)&3)<<22)
#define v_W0_BURST(x) (((x)&3)<<24)
#define v_W2_LUT_CTL(x) (((x)&1)<<26)
#define v_DSIP_LUT_CTL(x) (((x)&1)<<27)
#define v_HWC_REVERSED_COLOR(x) (((x)&1)<<28)
#define v_W1_AXI_OUTSTANDING2(x) (((x)&1)<<29)
#define v_W0_AXI_OUTSTANDING2(x) (((x)&1)<<30)
//LCDC_SWAP_CTRL
#define m_W1_565_RB_SWAP (1<<0)
#define m_W0_565_RB_SWAP (1<<1)
#define m_W0_YRGB_M8_SWAP (1<<2)
#define m_W0_YRGB_R_SHIFT_SWAP (1<<3)
#define m_W0_CBR_R_SHIFT_SWAP (1<<4)
#define m_W0_YRGB_16_SWAP (1<<5)
#define m_W0_YRGB_8_SWAP (1<<6)
#define m_W0_CBR_16_SWAP (1<<7)
#define m_W0_CBR_8_SWAP (1<<8)
#define m_W1_16_SWAP (1<<9)
#define m_W1_8_SWAP (1<<10)
#define m_W1_R_SHIFT_SWAP (1<<11)
#define m_OUTPUT_BG_SWAP (1<<12)
#define m_OUTPUT_RB_SWAP (1<<13)
#define m_OUTPUT_RG_SWAP (1<<14)
#define m_DELTA_SWAP (1<<15)
#define m_DUMMY_SWAP (1<<16)
#define m_W2_BYTE_SWAP (1<<17)
#define v_W1_565_RB_SWAP(x) (((x)&1)<<0)
#define v_W0_565_RB_SWAP(x) (((x)&1)<<1)
#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2)
#define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3)
#define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4)
#define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5)
#define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6)
#define v_W0_CBR_16_SWAP(x) (((x)&1)<<7)
#define v_W0_CBR_8_SWAP(x) (((x)&1)<<8)
#define v_W1_16_SWAP(x) (((x)&1)<<9)
#define v_W1_8_SWAP(x) (((x)&1)<<10)
#define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11)
#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12)
#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13)
#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14)
#define v_DELTA_SWAP(x) (((x)&1)<<15)
#define v_DUMMY_SWAP(x) (((x)&1)<<16)
#define v_W2_BYTE_SWAP(x) (((x)&1)<<17)
//LCDC_MCU_TIMING_CTRL
#define m_MCU_WRITE_PERIOD (31<<0)
#define m_MCU_CS_ST (31<<5)
#define m_MCU_CS_END (31<<10)
#define m_MCU_RW_ST (31<<15)
#define m_MCU_RW_END (31<<20)
#define m_MCU_HOLDMODE_SELECT (1<<27)
#define m_MCU_HOLDMODE_FRAME_ST (1<<28)
#define m_MCU_RS_SELECT (1<<29)
#define m_MCU_BYPASSMODE_SELECT (1<<30)
#define m_MCU_OUTPUT_SELECT (1<<31)
#define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0)
#define v_MCU_CS_ST(x) (((x)&31)<<5)
#define v_MCU_CS_END(x) (((x)&31)<<10)
#define v_MCU_RW_ST(x) (((x)&31)<<15)
#define v_MCU_RW_END(x) (((x)&31)<<20)
#define v_MCU_HOLD_STATUS(x) (((x)&1)<<26)
#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27)
#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28)
#define v_MCU_RS_SELECT(x) (((x)&1)<<29)
#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30)
#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31)
//LCDC_ BLEND_CTRL
#define m_HWC_BLEND_EN (1<<0)
#define m_W2_BLEND_EN (1<<1)
#define m_W1_BLEND_EN (1<<2)
#define m_W0_BLEND_EN (1<<3)
#define m_HWC_BLEND_FACTOR (15<<4)
#define m_W2_BLEND_FACTOR (0xff<<8)
#define m_W1_BLEND_FACTOR (0xff<<16)
#define m_W0_BLEND_FACTOR (0xff<<24)
#define v_HWC_BLEND_EN(x) (((x)&1)<<0)
#define v_W2_BLEND_EN(x) (((x)&1)<<1)
#define v_W1_BLEND_EN(x) (((x)&1)<<2)
#define v_W0_BLEND_EN(x) (((x)&1)<<3)
#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
#define m_KEYCOLOR (0xffffff<<0)
#define m_KEYCOLOR_B (0xff<<0)
#define m_KEYCOLOR_G (0xff<<8)
#define m_KEYCOLOR_R (0xff<<16)
#define m_COLORKEY_EN (1<<24)
#define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
#define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
#define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
#define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
#define v_COLORKEY_EN(x) (((x)&1)<<24)
//LCDC_DEFLICKER_SCL_OFFSET
#define m_W0_YRGB_VSD_OFFSET (0xff<<0)
#define m_W0_YRGB_VSP_OFFSET (0xff<<8)
#define m_W1_VSD_OFFSET (0xff<<16)
#define m_W1_VSP_OFFSET (0xff<<24)
#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
//LCDC_DSP_CTRL_REG0
#define m_DISPLAY_FORMAT (0xf<<0)
#define m_HSYNC_POLARITY (1<<4)
#define m_VSYNC_POLARITY (1<<5)
#define m_DEN_POLARITY (1<<6)
#define m_DCLK_POLARITY (1<<7)
#define m_COLOR_SPACE_CONVERSION (3<<8)
#define m_DITHER_UP_EN (1<<10)
#define m_DITHER_DOWN_MODE (1<<11)
#define m_DITHER_DOWN_EN (1<<12)
#define m_INTERLACE_FIELD_POLARITY (1<<13)
#define m_YUV_CLIP (1<<14)
#define m_W1_TRANSP_FROM (1<<15)
#define m_W0_TRANSP_FROM (1<<16)
#define m_W0_ON_TOP (1<<17)
#define m_W1_CLIP_EN (1<<18)
#define m_W0_CLIP_EN (1<<19)
#define m_W0_YCBR_PRIORITY_MODE (1<<20)
#define m_CBR_FILTER_656 (1<<21)
#define m_W2_CHIP_EN (1<<22)
#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0)
#define v_HSYNC_POLARITY(x) (((x)&1)<<4)
#define v_VSYNC_POLARITY(x) (((x)&1)<<5)
#define v_DEN_POLARITY(x) (((x)&1)<<6)
#define v_DCLK_POLARITY(x) (((x)&1)<<7)
#define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8)
#define v_DITHER_UP_EN(x) (((x)&1)<<10)
#define v_DITHER_DOWN_MODE(x) (((x)&1)<<11)
#define v_DITHER_DOWN_EN(x) (((x)&1)<<12)
#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
#define v_YUV_CLIP(x) (((x)&1)<<14)
#define v_W1_TRANSP_FROM(x) (((x)&1)<<15)
#define v_W0_TRANSP_FROM(x) (((x)&1)<<16)
#define v_W0_ON_TOP(x) (((x)&1)<<17)
#define v_W1_CLIP_EN(x) (((x)&1)<<18)
#define v_W0_CLIP_EN(x) (((x)&1)<<19)
#define v_W0_YCBR_PRIORITY_MODE(x) (((x)&1)<<20)
#define v_CBR_FILTER_656(x) (((x)&1)<<21)
#define v_W2_CHIP_EN(x) (((x)&1)<<22)
//LCDC_DSP_CTRL_REG1
#define m_BG_COLOR (0xffffff<<0)
#define m_BG_B (0xff<<0)
#define m_BG_G (0xff<<8)
#define m_BG_R (0xff<<16)
#define m_BLANK_MODE (1<<24)
#define m_BLACK_MODE (1<<25)
#define m_DISP_FILTER_FACTOR (3<<26)
#define m_DISP_FILTER_MODE (1<<28)
#define m_DISP_FILTER_EN (1<<29)
#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
#define v_BG_B(x) (((x)&0xff)<<0)
#define v_BG_G(x) (((x)&0xff)<<8)
#define v_BG_R(x) (((x)&0xff)<<16)
#define v_BLANK_MODE(x) (((x)&1)<<24)
#define v_BLACK_MODE(x) (((x)&1)<<25)
#define v_DISP_FILTER_FACTOR(x) (((x)&3)<<26)
#define v_DISP_FILTER_MODE(x) (((x)&1)<<28)
#define v_DISP_FILTER_EN(x) (((x)&1)<<29)
//LCDC_INT_STATUS
#define m_HOR_START (1<<0)
#define m_FRM_START (1<<1)
#define m_SCANNING_FLAG (1<<2)
#define m_HOR_STARTMASK (1<<3)
#define m_FRM_STARTMASK (1<<4)
#define m_SCANNING_MASK (1<<5)
#define m_HOR_STARTCLEAR (1<<6)
#define m_FRM_STARTCLEAR (1<<7)
#define m_SCANNING_CLEAR (1<<8)
#define m_SCAN_LINE_NUM (0x7ff<<9)
#define v_HOR_START(x) (((x)&1)<<0)
#define v_FRM_START(x) (((x)&1)<<1)
#define v_SCANNING_FLAG(x) (((x)&1)<<2)
#define v_HOR_STARTMASK(x) (((x)&1)<<3)
#define v_FRM_STARTMASK(x) (((x)&1)<<4)
#define v_SCANNING_MASK(x) (((x)&1)<<5)
#define v_HOR_STARTCLEAR(x) (((x)&1)<<6)
#define v_FRM_STARTCLEAR(x) (((x)&1)<<7)
#define v_SCANNING_CLEAR(x) (((x)&1)<<8)
#define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9)
//AXI MS ID
#define m_W0_YRGB_CH_ID (0xF<<0)
#define m_W0_CBR_CH_ID (0xF<<4)
#define m_W1_YRGB_CH_ID (0xF<<8)
#define m_W2_CH_ID (0xF<<12)
#define m_HWC_CH_ID (0xF<<16)
#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
#define v_W2_CH_ID(x) (((x)&0xF)<<12)
#define v_HWC_CH_ID(x) (((x)&0xF)<<16)
/* Low Bits Mask */
#define m_WORDLO (0xffff<<0)
#define m_WORDHI (0xffff<<16)
#define v_WORDLO(x) (((x)&0xffff)<<0)
#define v_WORDHI(x) (((x)&0xffff)<<16)
#define m_BIT11LO (0x7ff<<0)
#define m_BIT11HI (0x7ff<<16)
#define v_BIT11LO(x) (((x)&0x7ff)<<0)
#define v_BIT11HI(x) (((x)&0x7ff)<<16)
#define m_BIT12LO (0xfff<<0)
#define m_BIT12HI (0xfff<<16)
#define v_BIT12LO(x) (((x)&0xfff)<<0)
#define v_BIT12HI(x) (((x)&0xfff)<<16)
#define m_VIRWIDTH (0xffff<<0)
#define m_VIRHEIGHT (0xffff<<16)
#define v_VIRWIDTH(x) (((x)&0xffff)<<0)
#define v_VIRHEIGHT(x) (((x)&0xffff)<<16)
#define m_ACTWIDTH (0xffff<<0)
#define m_ACTHEIGHT (0xffff<<16)
#define v_ACTWIDTH(x) (((x)&0xffff)<<0)
#define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
#define m_VIRST_X (0xffff<<0)
#define m_VIRST_Y (0xffff<<16)
#define v_VIRST_X(x) (((x)&0xffff)<<0)
#define v_VIRST_Y(x) (((x)&0xffff)<<16)
#define m_PANELST_X (0x3ff<<0)
#define m_PANELST_Y (0x3ff<<16)
#define v_PANELST_X(x) (((x)&0x3ff)<<0)
#define v_PANELST_Y(x) (((x)&0x3ff)<<16)
#define m_PANELWIDTH (0x3ff<<0)
#define m_PANELHEIGHT (0x3ff<<16)
#define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
#define m_HWC_B (0xff<<0)
#define m_HWC_G (0xff<<8)
#define m_HWC_R (0xff<<16)
#define m_W0_YRGB_HSP_OFFSET (0xff<<24)
#define m_W0_YRGB_HSD_OFFSET (0xff<<24)
#define v_HWC_B(x) (((x)&0xff)<<0)
#define v_HWC_G(x) (((x)&0xff)<<8)
#define v_HWC_R(x) (((x)&0xff)<<16)
#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
//Panel display scanning
#define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
#define m_PANEL_END (0x3ff<<0)
#define m_PANEL_START (0x3ff<<16)
#define v_PANEL_END(x) (((x)&0x3ff)<<0)
#define v_PANEL_START(x) (((x)&0x3ff)<<16)
#define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
//-----------
#define m_HSCALE_FACTOR (0xffff<<0)
#define m_VSCALE_FACTOR (0xffff<<16)
#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
#define m_W0_CBR_HSD_OFFSET (0xff<<0)
#define m_W0_CBR_HSP_OFFSET (0xff<<8)
#define m_W0_CBR_VSD_OFFSET (0xff<<16)
#define m_W0_CBR_VSP_OFFSET (0xff<<24)
#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
#define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
#define FB0_IOCTL_SET_PANEL 0x6002
#ifdef CONFIG_FB_WIMO
#define FB_WIMO_FLAG
#endif
#ifdef FB_WIMO_FLAG
#define FB0_IOCTL_SET_BUF 0x6017
#define FB0_IOCTL_COPY_CURBUF 0x6018
#define FB0_IOCTL_CLOSE_BUF 0x6019
#endif
#define FB1_IOCTL_GET_PANEL_SIZE 0x5001
#define FB1_IOCTL_SET_YUV_ADDR 0x5002
//#define FB1_TOCTL_SET_MCU_DIR 0x5003
#define FB1_IOCTL_SET_ROTATE 0x5003
#define FB1_IOCTL_SET_I2P_ODD_ADDR 0x5005
#define FB1_IOCTL_SET_I2P_EVEN_ADDR 0x5006
#define FB1_IOCTL_SET_WIN0_TOP 0x5018
/********************************************************************
** 结构定义 *
********************************************************************/
/* LCDC的寄存器结构 */
typedef volatile struct tagLCDC_REG
{
/* offset 0x00~0xc0 */
unsigned int SYS_CONFIG; //0x00 SYSTEM configure register
unsigned int SWAP_CTRL; //0x04 Data SWAP control
unsigned int MCU_TIMING_CTRL; //0x08 MCU TIMING control register
unsigned int BLEND_CTRL; //0x0c Blending control register
unsigned int WIN0_COLOR_KEY_CTRL; //0x10 Win0 blending control register
unsigned int WIN1_COLOR_KEY_CTRL; //0x14 Win1 blending control register
unsigned int WIN2_VIR; //0x18 WIN2 virtual display width
unsigned int DSP_CTRL0; //0x1c Display control register0
unsigned int DSP_CTRL1; //0x20 Display control register1
unsigned int INT_STATUS; //0x24 Interrupt status register
unsigned int WIN0_VIR; //0x28 WIN0 virtual display width/height
unsigned int WIN0_YRGB_MST; //0x2c Win0 active YRGB memory start address
unsigned int WIN0_CBR_MST; //0x30 Win0 active Cbr memory start address
unsigned int WIN0_ACT_INFO; //0x34 Win0 active window width/height
unsigned int WIN0_DSP_ST; //0x38 Win0 display start point on panel
unsigned int WIN0_DSP_INFO; //0x3c Win0 display width/height on panel
unsigned int WIN1_VIR; //0x40 Win1 virtual display width/height
unsigned int WIN1_YRGB_MST; //0x44 Win1 active memory start address
unsigned int WIN1_DSP_INFO; //0x48 Win1 display width/height on panel
unsigned int WIN1_DSP_ST; //0x4c Win1 display start point on panel
unsigned int WIN2_MST; //0X50 Win2 memory start address
unsigned int WIN2_DSP_INFO; //0x54 Win1 display width/height on panel
unsigned int WIN2_DSP_ST; //0x58 Win1 display start point on panel
unsigned int HWC_MST; //0x5C HWC memory start address
unsigned int HWC_DSP_ST; //0x60 HWC display start point on panel
unsigned int HWC_COLOR_LUT0; //0x64 Hardware cursor color 2’b01 look up table 0
unsigned int HWC_COLOR_LUT1; //0x68 Hardware cursor color 2’b10 look up table 1
unsigned int HWC_COLOR_LUT2; //0x6c Hardware cursor color 2’b11 look up table 2
unsigned int DSP_HTOTAL_HS_END; //0x70 Panel scanning horizontal width and hsync pulse end point
unsigned int DSP_HACT_ST_END; //0x74 Panel active horizontal scanning start/end point
unsigned int DSP_VTOTAL_VS_END; //0x78 Panel scanning vertical height and vsync pulse end point
unsigned int DSP_VACT_ST_END; //0x7c Panel active vertical scanning start/end point
unsigned int DSP_VS_ST_END_F1; //0x80 Vertical scanning start point and vsync pulse end point of even filed in interlace mode
unsigned int DSP_VACT_ST_END_F1; //0x84 Vertical scanning active start/end point of even filed in interlace mode
unsigned int WIN0_SCL_FACTOR_YRGB; //0x88 Win0 YRGB scaling down factor setting
unsigned int WIN0_SCL_FACTOR_CBR; //0x8c Win0 YRGB scaling up factor setting
unsigned int WIN0_SCL_OFFSET; //0x90 Win0 Cbr scaling start point offset
unsigned int FIFO_WATER_MARK; //0x94 Fifo water mark
unsigned int AXI_MS_ID; //0x98 Axi master ID
unsigned int reserved0; //0x9c
unsigned int REG_CFG_DONE; //0xa0 REGISTER CONFIG FINISH
unsigned int reserved1[(0x100-0xa4)/4];
unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port
unsigned int reserved2[(0x200-0x104)/4];
unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port
} LCDC_REG, *pLCDC_REG;
//roate
#define ROTATE_0 0
#define ROTATE_90 90
#define ROTATE_180 180
#define ROTATE_270 270
#define X_MIRROR (1<<10)
#define Y_MIRROR (1<<11)
extern void __init rk29_add_device_lcdc(void);
extern int mcu_ioctl(unsigned int cmd, unsigned long arg);
#define RK29FB_EVENT_HDMI_ON 1
#define RK29FB_EVENT_HDMI_OFF 2
#define RK29FB_EVENT_FB1_ON 3
#define RK29FB_EVENT_FB1_OFF 4
#include <linux/notifier.h>
int rk29fb_register_notifier(struct notifier_block *nb);
int rk29fb_unregister_notifier(struct notifier_block *nb);
#endif