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net: phy: mediatek-ge-soc: Fix coding style

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This patch fixes spelling errors, re-arrange vars with
reverse Xmas tree and remove unnecessary parens in
mediatek-ge-soc.c.

Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
This commit is contained in:
SkyLake.Huang 2024-10-17 11:22:11 +08:00 committed by Andrew Lunn
parent d64113c6bb
commit b544223bec
1 changed files with 20 additions and 18 deletions
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38
drivers/net/phy/mediatek-ge-soc.c
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@ -408,16 +408,17 @@ static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
{
int i;
int bias[16] = {};
const int vals_9461[16] = { 7, 1, 4, 7,
7, 1, 4, 7,
7, 1, 4, 7,
7, 1, 4, 7 };
const int vals_9481[16] = { 10, 6, 6, 10,
10, 6, 6, 10,
10, 6, 6, 10,
10, 6, 6, 10 };
const int vals_9461[16] = { 7, 1, 4, 7,
7, 1, 4, 7,
7, 1, 4, 7,
7, 1, 4, 7 };
int bias[16] = {};
int i;
switch (phydev->drv->phy_id) {
case MTK_GPHY_ID_MT7981:
/* We add some calibration to efuse values
@ -1069,10 +1070,10 @@ static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
static int mt798x_phy_calibration(struct phy_device *phydev)
{
int ret = 0;
u32 *buf;
size_t len;
struct nvmem_cell *cell;
int ret = 0;
size_t len;
u32 *buf;
cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
if (IS_ERR(cell)) {
@ -1210,14 +1211,15 @@ static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
}
static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
BIT(TRIGGER_NETDEV_LINK) |
BIT(TRIGGER_NETDEV_LINK_10) |
BIT(TRIGGER_NETDEV_LINK_100) |
BIT(TRIGGER_NETDEV_LINK_1000) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX));
static const unsigned long supported_triggers =
BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
BIT(TRIGGER_NETDEV_LINK) |
BIT(TRIGGER_NETDEV_LINK_10) |
BIT(TRIGGER_NETDEV_LINK_100) |
BIT(TRIGGER_NETDEV_LINK_1000) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
unsigned long rules)
@ -1415,7 +1417,7 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev)
* LED_C and LED_D respectively. At the same time those pins are used to
* bootstrap configuration of the reference clock source (LED_A),
* DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
* In practise this is done using a LED and a resistor pulling the pin
* In practice this is done using a LED and a resistor pulling the pin
* either to GND or to VIO.
* The detected value at boot time is accessible at run-time using the
* TPBANK0 register located in the gpio base of the pinctrl, in order