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TI K3 device tree updates for v6.11
Generic Fixups/Cleanups: - main_pktdma reg ranges fixes - dtbs_check warning cleanups with addition of cpsw-mac-efuse node and dropping "syscon", "simple-mfd" compatibles in favor of simple-bus - Disable McASP FIFOs across SoCs for better latency - Add memory node to bootloader stage with bootph-all - Restructure am62p and j722s dtsi for share nodes across these SoCs - DT warning fixes around USB type-C connector node (AM62/AM62P) SoC Specific features and Fixes: AM62 - GPMC and ELM addition AM62A - Enable RTC by default - Crypto accelerator support AM64 and AM65 - PRU system event support AM69/J784S4: - CPSW2G and CPSW9G addition with QSGMII and UXSGMII board support - PCIe, USB, McASP, EHRPWM node additions AM67/J722s - Fix to update GPIO count - Add gpio-ranges definition - McASP support for audio - PCIe, USB, Serdes support Board Specific features and fixes: AM62 - am62x-phyboard-lyra carrier board support - am625-verdin: nau8822 PLL support - sk: CMA node addition - lp-sk: NAND expansion card overlay AM62A - New phyboard-lyra-am62ax from phytec - CMA node addition AM64: - phycore-board: PMIC support - hummingbird-t: RS485 RTS pin polarity update - am6xx-phycore-som: overlays for variants w/o SPI, RTC, ETH PHY or w/ QSPI - EVM: GPMC NAND expansion card overlay - EVM: ICSSG ethernet MII mode overlay support - SK: power supply temp sensors support AM68 - SK: PMIC, OSPI J721e - SK: MCAN Support - Overlay for infotainment expansion board AM69/J784S4 - EVM: PCIe RC/EP, USB3, MCAN support - SK: PMIC support -----BEGIN PGP SIGNATURE----- iQFDBAABCAAuFiEEyRC2zAhGcGjrhiNExEYeRXyRFuMFAmaICFIQHHZpZ25lc2hy QHRpLmNvbQAKCRDERh5FfJEW49SrB/dQ8b2v+JgzPBkOsV9ig96/BFJCOj8WfPfI quUpTkmsRGfD+dRAwBSlfFk/ulwXNf2i+ah3D5ITyplTMn78VYiPWFEMDoH4Uq7+ CHX0hdYneBv4AwhQycQQcdPKrdP2D8vSFoldBMVNh9Tdhvx3RmM4JEhbsBq45SXx QLr8CQkKEYiwxMvnacD92ymhUQdzQC9K5W+J9MIxQAdnq9nc3sosgJbsTIDn1EEu ThFV5OK6zMfVSOIsvtUafv/UdlYmb9xMDZwvGgqa2wUFhdDy7bKj5spzQSQJmoH7 ZJX3Wzfk1HPcPrU8j9anB9xP9WEFn+uzJEwsoscjFdiFL6RNJ3U= =tJcy -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmaL+PkACgkQYKtH/8kJ Uiex0A/5AVhK/PQ3Hfg8YMf+Z00A6w9LENtF/KowSlIook4eU/EgvMKO6m1R7ofJ ochJyHVXETD9S8ms+zABa0mAWUtvAtMn7x7RJuT+PrTJyLkHgx1VRCMoW3YxOqyq Y5k1Pec5/SwPRDKngcTeh1w8bCghj9l53j5/E1LtR01UmfwDWTo3m2DBghbI/+YK hvRIqgSxi5MAqXNNTJeDIxb6arR77NZ5CStfH6tj60B9RJWqJQeKfeMBSyg1ZYnv qBVfWdYfdkdVu8SR/W8xeYnOGM6E5sG0PfhnUH0WX2pgloL40ZXPOGw0lCNuND3c hDY+ZLGNSKtCu65JaiMF7m68tY2DnpjwAngzA+f1Ga5JP+UDXWfMqZMpnoHRCSpX 9qGmVv45xXObGDmqETPJuElw2NTz9h6CCyrUjDpAmARAbdsK4BQ6amoI+eQTAfO3 WxwepdU8rvpw8EUyKbphOdPShXdWu7DK1hVp82+Gjr1p4rYJwhQSAi91ajUubk0Z w8TLYKNjb685710xIwtC/pZejzUbsz3jkkb/022cHH6po1/VwhZ0OZXy1L6/nOLN XJmNDdpi/rhI939GNLla0OAzDlXqBe8dfiE2XQnlBWV534PTxbh0OlLM94lESG1G svcjd0IKrWi7xPnKr2Q+/IcIRIUjQHMsvzpk0fZn8CvY6gWIg1s= =7zo8 -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt TI K3 device tree updates for v6.11 Generic Fixups/Cleanups: - main_pktdma reg ranges fixes - dtbs_check warning cleanups with addition of cpsw-mac-efuse node and dropping "syscon", "simple-mfd" compatibles in favor of simple-bus - Disable McASP FIFOs across SoCs for better latency - Add memory node to bootloader stage with bootph-all - Restructure am62p and j722s dtsi for share nodes across these SoCs - DT warning fixes around USB type-C connector node (AM62/AM62P) SoC Specific features and Fixes: AM62 - GPMC and ELM addition AM62A - Enable RTC by default - Crypto accelerator support AM64 and AM65 - PRU system event support AM69/J784S4: - CPSW2G and CPSW9G addition with QSGMII and UXSGMII board support - PCIe, USB, McASP, EHRPWM node additions AM67/J722s - Fix to update GPIO count - Add gpio-ranges definition - McASP support for audio - PCIe, USB, Serdes support Board Specific features and fixes: AM62 - am62x-phyboard-lyra carrier board support - am625-verdin: nau8822 PLL support - sk: CMA node addition - lp-sk: NAND expansion card overlay AM62A - New phyboard-lyra-am62ax from phytec - CMA node addition AM64: - phycore-board: PMIC support - hummingbird-t: RS485 RTS pin polarity update - am6xx-phycore-som: overlays for variants w/o SPI, RTC, ETH PHY or w/ QSPI - EVM: GPMC NAND expansion card overlay - EVM: ICSSG ethernet MII mode overlay support - SK: power supply temp sensors support AM68 - SK: PMIC, OSPI J721e - SK: MCAN Support - Overlay for infotainment expansion board AM69/J784S4 - EVM: PCIe RC/EP, USB3, MCAN support - SK: PMIC support * tag 'ti-k3-dt-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (89 commits) arm64: dts: ti: k3-am62a7-sk: Reserve 576MiB of global CMA arm64: dts: ti: k3-am62x-sk-common: Reserve 128MiB of global CMA arm64: dts: ti: k3-am62x-sk-common: Fix graph_child_address warns arm64: dts: ti: k3-am62p5-sk: fix graph_child_address warnings arm64: dts: ti: k3-j722s: Add gpio-ranges properties arm64: dts: ti: k3-am62p: Add gpio-ranges properties arm64: dts: ti: k3-pinctrl: Define a generic GPIO MUX Mode arm64: dts: ti: k3-am62: Add cpsw-mac-efuse node to wkup_conf arm64: dts: ti: k3-am62a: Add cpsw-mac-efuse node to wkup_conf arm64: dts: ti: k3-j784s4: Add cpsw-mac-efuse node to mcu_conf arm64: dts: ti: k3-j721s2: Add cpsw-mac-efuse node to mcu_conf arm64: dts: ti: k3-j721e: Add cpsw-mac-efuse node to mcu_conf arm64: dts: ti: k3-j7200: Add cpsw-mac-efuse node to mcu_conf arm64: dts: ti: k3-am65: Add cpsw-mac-efuse node to mcu_conf arm: dts: k3-am642-evm-nand: Add bootph-all to NAND related nodes arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM62Ax dt-bindings: arm: ti: Add bindings for PHYTEC AM62Ax based hardware arm64: dts: ti: Add am62x-phyboard-lyra carrier board arm64: dts: ti: k3-am62a: Enable AUDIO_REFCLKx arm64: dts: ti: k3-j784s4-evm: Enable analog audio support ... Link: https://lore.kernel.org/r/37f251a1-f3bd-402f-ab22-cf786c3871d7@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
b4f8192afb
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@ -25,6 +25,12 @@ properties:
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- ti,am62a7-sk
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- const: ti,am62a7
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- description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra
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items:
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- const: phytec,am62a7-phyboard-lyra-rdk
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- const: phytec,am62a-phycore-som
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- const: ti,am62a7
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- description: K3 AM62P5 SoC and Boards
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items:
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- enum:
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@ -22,11 +22,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-mallow.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
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# Boards with AM62Ax SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb
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# Boards with AM62Px SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
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@ -44,16 +47,26 @@ k3-am642-hummingboard-t-usb3-dtbs := \
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k3-am642-hummingboard-t.dtb k3-am642-hummingboard-t-usb3.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-usb3.dtb
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k3-am642-evm-nand-dtbs := k3-am642-evm.dtb k3-am642-evm-nand.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-nand.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
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# Common overlays for the phyCORE-AM6* family of boards
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dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-eth-phy.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-rtc.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-spi-nor.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-qspi-nor.dtbo
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# Boards with AM65x SoC
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k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \
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k3-am654-base-board-rocktech-rk101-panel.dtbo \
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@ -81,6 +94,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb
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# Boards with J721e SoC
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k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board-infotainment.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
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@ -101,14 +115,27 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
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# Boards with J784s4 SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
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# Build time test only, enabled by CONFIG_OF_ALL_DTBS
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k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
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k3-am625-beagleplay-csi2-ov5640.dtbo
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k3-am625-beagleplay-csi2-tevi-ov5640-dtbs := k3-am625-beagleplay.dtb \
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k3-am625-beagleplay-csi2-tevi-ov5640.dtbo
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k3-am625-phyboard-lyra-1-4-ghz-opp.dtbs := k3-am625-phyboard-lyra-rdk.dtb \
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k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo
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k3-am625-phyboard-lyra-disable-eth-phy-dtbs := k3-am625-phyboard-lyra-rdk.dtb \
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k3-am6xx-phycore-disable-eth-phy.dtbo
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k3-am625-phyboard-lyra-disable-rtc-dtbs := k3-am625-phyboard-lyra-rdk.dtb \
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k3-am6xx-phycore-disable-rtc.dtbo
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k3-am625-phyboard-lyra-disable-spi-nor-dtbs := k3-am625-phyboard-lyra-rdk.dtb \
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k3-am6xx-phycore-disable-spi-nor.dtbo
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k3-am625-phyboard-lyra-gpio-fan-dtbs := k3-am625-phyboard-lyra-rdk.dtb \
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k3-am62x-phyboard-lyra-gpio-fan.dtbo
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k3-am625-phyboard-lyra-qspi-nor-dtbs := k3-am625-phyboard-lyra-rdk.dtb \
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k3-am6xx-phycore-qspi-nor.dtbo
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k3-am625-sk-csi2-imx219-dtbs := k3-am625-sk.dtb \
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k3-am62x-sk-csi2-imx219.dtbo
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k3-am625-sk-csi2-ov5640-dtbs := k3-am625-sk.dtb \
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@ -132,8 +159,20 @@ k3-am62p5-sk-csi2-tevi-ov5640-dtbs := k3-am62p5-sk.dtb \
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k3-am62x-sk-csi2-tevi-ov5640.dtbo
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k3-am642-evm-icssg1-dualemac-dtbs := \
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k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo
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k3-am642-evm-icssg1-dualemac-mii-dtbs := \
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k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac-mii.dtbo
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k3-am642-phyboard-electra-disable-eth-phy-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-eth-phy.dtbo
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k3-am642-phyboard-electra-disable-rtc-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-rtc.dtbo
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k3-am642-phyboard-electra-disable-spi-nor-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-spi-nor.dtbo
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k3-am642-phyboard-electra-qspi-nor-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-qspi-nor.dtbo
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k3-am642-phyboard-electra-gpio-fan-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo
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k3-am642-phyboard-electra-pcie-usb2-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo
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k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \
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k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
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k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \
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@ -142,12 +181,20 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \
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k3-j721e-sk-csi2-dual-imx219.dtbo
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k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \
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k3-j721e-sk-csi2-dual-imx219.dtbo
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k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \
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k3-j721e-common-proc-board-infotainment.dtbo
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k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
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k3-j721e-evm-pcie0-ep.dtbo
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k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
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k3-j721e-sk-csi2-dual-imx219.dtbo
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k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
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k3-j721s2-evm-pcie1-ep.dtbo
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k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \
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k3-j784s4-evm-pcie0-pcie1-ep.dtbo
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k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
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k3-j784s4-evm-quad-port-eth-exp1.dtbo
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k3-j784s4-evm-usxgmii-exp1-exp2-dtbs := k3-j784s4-evm.dtb \
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k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
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dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
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k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
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k3-am625-sk-csi2-imx219.dtb \
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@ -162,17 +209,23 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
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k3-am62p5-sk-csi2-ov5640.dtb \
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k3-am62p5-sk-csi2-tevi-ov5640.dtb \
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k3-am642-evm-icssg1-dualemac.dtb \
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k3-am642-evm-icssg1-dualemac-mii.dtb \
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k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
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k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
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k3-am68-sk-base-board-csi2-dual-imx219.dtb \
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k3-am69-sk-csi2-dual-imx219.dtb \
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k3-j721e-common-proc-board-infotainment.dtb \
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k3-j721e-evm-pcie0-ep.dtb \
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k3-j721e-sk-csi2-dual-imx219.dtb \
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k3-j721s2-evm-pcie1-ep.dtb
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k3-j721s2-evm-pcie1-ep.dtb \
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k3-j784s4-evm-pcie0-pcie1-ep.dtb \
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k3-j784s4-evm-quad-port-eth-exp1.dtb \
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k3-j784s4-evm-usxgmii-exp1-exp2.dtb
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# Enable support for device-tree overlays
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DTC_FLAGS_k3-am625-beagleplay += -@
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DTC_FLAGS_k3-am625-phyboard-lyra-rdk += -@
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DTC_FLAGS_k3-am62a7-phyboard-lyra-rdk += -@
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DTC_FLAGS_k3-am625-sk += -@
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DTC_FLAGS_k3-am62-lp-sk += -@
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DTC_FLAGS_k3-am62a7-sk += -@
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@ -186,3 +239,4 @@ DTC_FLAGS_k3-am69-sk += -@
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DTC_FLAGS_k3-j721e-common-proc-board += -@
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DTC_FLAGS_k3-j721e-sk += -@
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DTC_FLAGS_k3-j721s2-common-proc-board += -@
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DTC_FLAGS_k3-j784s4-evm += -@
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|||
116
arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso
Normal file
116
arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
&mcasp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
gpmc0_pins_default: gpmc0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
|
||||
AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */
|
||||
AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (L20) GPMC0_AD2 */
|
||||
AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (L21) GPMC0_AD3 */
|
||||
AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (M21) GPMC0_AD4 */
|
||||
AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (L17) GPMC0_AD5 */
|
||||
AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (L18) GPMC0_AD6 */
|
||||
AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (M20) GPMC0_AD7 */
|
||||
AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (P21) GPMC0_WAIT0 */
|
||||
AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (J18) GPMC0_CSn0 */
|
||||
AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (K20) GPMC0_ADVn_ALE */
|
||||
AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (K21) GPMC0_OEn_REn */
|
||||
AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (J17) GPMC0_WEn */
|
||||
AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (K17) GPMC0_BE0n_CLE */
|
||||
AM62X_IOPAD(0x00a0, PIN_OUTPUT, 0) /* (J20) GPMC0_WPn */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&elm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpmc0_pins_default>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,am64-nand";
|
||||
reg = <0 0 64>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc0>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
||||
ti,nand-xfer-type = "prefetch-polled";
|
||||
ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
|
||||
ti,elm-id = <&elm0>;
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <40>;
|
||||
gpmc,cs-wr-off-ns = <40>;
|
||||
gpmc,adv-on-ns = <0>;
|
||||
gpmc,adv-rd-off-ns = <25>;
|
||||
gpmc,adv-wr-off-ns = <25>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <20>;
|
||||
gpmc,oe-on-ns = <3>;
|
||||
gpmc,oe-off-ns = <30>;
|
||||
gpmc,access-ns = <30>;
|
||||
gpmc,rd-cycle-ns = <40>;
|
||||
gpmc,wr-cycle-ns = <40>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "NAND.tiboot3";
|
||||
reg = <0x00000000 0x00200000>; /* 2M */
|
||||
};
|
||||
partition@200000 {
|
||||
label = "NAND.tispl";
|
||||
reg = <0x00200000 0x00200000>; /* 2M */
|
||||
};
|
||||
partition@400000 {
|
||||
label = "NAND.tiboot3.backup"; /* 2M */
|
||||
reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
|
||||
};
|
||||
partition@600000 {
|
||||
label = "NAND.u-boot";
|
||||
reg = <0x00600000 0x00400000>; /* 4M */
|
||||
};
|
||||
partition@a00000 {
|
||||
label = "NAND.u-boot-env";
|
||||
reg = <0x00a00000 0x00040000>; /* 256K */
|
||||
};
|
||||
partition@a40000 {
|
||||
label = "NAND.u-boot-env.backup";
|
||||
reg = <0x00a40000 0x00040000>; /* 256K */
|
||||
};
|
||||
partition@a80000 {
|
||||
label = "NAND.file-system";
|
||||
reg = <0x00a80000 0x3f580000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -228,3 +228,7 @@ ldo4_reg: ldo4 {
|
|||
&tlv320aic3106 {
|
||||
DVDD-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&gpmc0 {
|
||||
ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -141,8 +141,8 @@ main_pktdma: dma-controller@485c0000 {
|
|||
compatible = "ti,am64-dmss-pktdma";
|
||||
reg = <0x00 0x485c0000 0x00 0x100>,
|
||||
<0x00 0x4a800000 0x00 0x20000>,
|
||||
<0x00 0x4aa00000 0x00 0x40000>,
|
||||
<0x00 0x4b800000 0x00 0x400000>,
|
||||
<0x00 0x4aa00000 0x00 0x20000>,
|
||||
<0x00 0x4b800000 0x00 0x200000>,
|
||||
<0x00 0x485e0000 0x00 0x10000>,
|
||||
<0x00 0x484a0000 0x00 0x2000>,
|
||||
<0x00 0x484c0000 0x00 0x2000>,
|
||||
|
|
@ -207,10 +207,6 @@ k3_reset: reset-controller {
|
|||
crypto: crypto@40900000 {
|
||||
compatible = "ti,am62-sa3ul";
|
||||
reg = <0x00 0x40900000 0x00 0x1200>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
|
||||
|
||||
dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
|
||||
<&main_pktdma 0x7507 0>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
|
|
@ -739,7 +735,7 @@ cpsw_port1: port@1 {
|
|||
label = "port1";
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
ti,syscon-efuse = <&wkup_conf 0x200>;
|
||||
ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
|
||||
};
|
||||
|
||||
cpsw_port2: port@2 {
|
||||
|
|
@ -1057,4 +1053,33 @@ dphy0: phy@30110000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gpmc0: memory-controller@3b000000 {
|
||||
compatible = "ti,am64-gpmc";
|
||||
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 80 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x00 0x03b000000 0x00 0x400>,
|
||||
<0x00 0x050000000 0x00 0x8000000>;
|
||||
reg-names = "cfg", "data";
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpmc,num-cs = <3>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
elm0: ecc@25010000 {
|
||||
compatible = "ti,am64-elm";
|
||||
reg = <0x00 0x25010000 0x00 0x2000>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 54 0>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ sound {
|
|||
simple-audio-card,bitclock-master = <&codec_dai>;
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,frame-master = <&codec_dai>;
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,name = "verdin-nau8822";
|
||||
simple-audio-card,routing =
|
||||
"Headphones", "LHP",
|
||||
|
|
@ -34,7 +35,6 @@ sound {
|
|||
"Line", "Line In";
|
||||
|
||||
codec_dai: simple-audio-card,codec {
|
||||
clocks = <&audio_refclk1>;
|
||||
sound-dai = <&nau8822_1a>;
|
||||
};
|
||||
|
||||
|
|
@ -107,6 +107,8 @@ nau8822_1a: audio-codec@1a {
|
|||
reg = <0x1a>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2s1_mclk>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&audio_refclk1>;
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1364,8 +1364,6 @@ &mcasp0 {
|
|||
0 0 0 0
|
||||
>;
|
||||
tdm-slots = <2>;
|
||||
rx-num-evt = <32>;
|
||||
tx-num-evt = <32>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1382,8 +1380,6 @@ &mcasp1 {
|
|||
0 0 0 0
|
||||
>;
|
||||
tdm-slots = <2>;
|
||||
rx-num-evt = <32>;
|
||||
tx-num-evt = <32>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -22,6 +22,11 @@ chipid: chipid@14 {
|
|||
reg = <0x14 0x4>;
|
||||
};
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
};
|
||||
|
||||
usb0_phy_ctrl: syscon@4008 {
|
||||
compatible = "ti,am62-usb-phy-ctrl", "syscon";
|
||||
reg = <0x4008 0x4>;
|
||||
|
|
|
|||
|
|
@ -68,11 +68,13 @@ cbass_main: bus@f0000 {
|
|||
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
|
||||
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
|
||||
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
|
||||
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
|
||||
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
|
||||
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
|
||||
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
|
||||
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
|
|
|
|||
|
|
@ -924,6 +924,4 @@ &mcasp1 {
|
|||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 PHYTEC America LLC
|
||||
* Author: Nathan Morrisson <nmorrisson@phytec.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&vdd_core {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
};
|
||||
|
||||
&a53_opp_table {
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
};
|
||||
};
|
||||
|
|
@ -7,477 +7,12 @@
|
|||
* https://www.phytec.com/product/phyboard-am62x
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am625.dtsi"
|
||||
#include "k3-am62-phycore-som.dtsi"
|
||||
#include "k3-am62x-phyboard-lyra.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "phytec,am625-phyboard-lyra-rdk",
|
||||
"phytec,am62-phycore-som", "ti,am625";
|
||||
model = "PHYTEC phyBOARD-Lyra AM625";
|
||||
|
||||
aliases {
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
mmc1 = &sdhci1;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
};
|
||||
|
||||
can_tc1: can-phy0 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <8000000>;
|
||||
standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
hdmi0: connector-hdmi {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&sii9022_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys_pins_default>;
|
||||
|
||||
key-home {
|
||||
label = "home";
|
||||
linux,code = <KEY_HOME>;
|
||||
gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
key-menu {
|
||||
label = "menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "phyBOARD-Lyra";
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Mic Jack",
|
||||
"Headphone", "Headphone Jack",
|
||||
"Speaker", "External Speaker";
|
||||
simple-audio-card,routing =
|
||||
"MIC3R", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT",
|
||||
"External Speaker", "SPOP",
|
||||
"External Speaker", "SPOM";
|
||||
simple-audio-card,format = "dsp_b";
|
||||
simple-audio-card,bitclock-master = <&sound_master>;
|
||||
simple-audio-card,frame-master = <&sound_master>;
|
||||
simple-audio-card,bitclock-inversion;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&mcasp2>;
|
||||
};
|
||||
|
||||
sound_master: simple-audio-card,codec {
|
||||
sound-dai = <&audio_codec>;
|
||||
clocks = <&audio_refclk1>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
|
||||
|
||||
led-1 {
|
||||
gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc1";
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-vcc-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_mmc: regulator-vcc-3v3-mmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3_MMC";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_sw: regulator-vcc-3v3-sw {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3_SW";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
|
||||
>;
|
||||
};
|
||||
|
||||
gpio_keys_pins_default: gpio-keys-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
|
||||
>;
|
||||
};
|
||||
|
||||
gpio_exp_int_pins_default: gpio-exp-int-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
|
||||
>;
|
||||
};
|
||||
|
||||
hdmi_int_pins_default: hdmi-int-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_dss0_pins_default: main-dss0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
|
||||
AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
|
||||
AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
|
||||
AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
|
||||
AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
|
||||
AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
|
||||
AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
|
||||
AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
|
||||
AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
|
||||
AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
|
||||
AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
|
||||
AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
|
||||
AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
|
||||
AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
|
||||
AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
|
||||
AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
|
||||
AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
|
||||
AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
|
||||
AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
|
||||
AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
|
||||
AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan0_pins_default: main-mcan0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */
|
||||
AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcasp2_pins_default: main-mcasp2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x070, PIN_INPUT, 3) /* (T24) GPMC0_AD13.MCASP2_ACLKX */
|
||||
AM62X_IOPAD(0x06c, PIN_INPUT, 3) /* (T22) GPMC0_AD12.MCASP2_AFSX */
|
||||
AM62X_IOPAD(0x064, PIN_OUTPUT, 3) /* (T25) GPMC0_AD10.MCASP2_AXR2 */
|
||||
AM62X_IOPAD(0x068, PIN_INPUT, 3) /* (R21) GPMC0_AD11.MCASP2_AXR3 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */
|
||||
AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */
|
||||
AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */
|
||||
AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */
|
||||
AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */
|
||||
AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
|
||||
AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_rgmii2_pins_default: main-rgmii2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
|
||||
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
|
||||
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
|
||||
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
|
||||
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
|
||||
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
|
||||
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
|
||||
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
|
||||
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
|
||||
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
|
||||
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
|
||||
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
|
||||
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
|
||||
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
|
||||
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
|
||||
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb1_pins_default: main-usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
user_leds_pins_default: user-leds-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy3>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_dss0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dss_ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* VP2: DPI/HDMI Output */
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dpi1_out: endpoint {
|
||||
remote-endpoint = <&sii9022_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
audio_codec: audio-codec@18 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&audio_ext_refclk1_pins_default>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ti,tlv320aic3007";
|
||||
reg = <0x18>;
|
||||
ai3x-micbias-vg = <2>;
|
||||
|
||||
AVDD-supply = <&vcc_3v3_sw>;
|
||||
IOVDD-supply = <&vcc_3v3_sw>;
|
||||
DRVDD-supply = <&vcc_3v3_sw>;
|
||||
DVDD-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
gpio_exp: gpio-expander@21 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_exp_int_pins_default>;
|
||||
compatible = "nxp,pcf8574";
|
||||
reg = <0x21>;
|
||||
interrupt-parent = <&main_gpio1>;
|
||||
interrupts = <49 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-line-names = "", "GPIO1_CAN0_nEN",
|
||||
"GPIO2_LED2", "GPIO3_LVDS_GPIO",
|
||||
"GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN",
|
||||
"GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET";
|
||||
};
|
||||
|
||||
usb-pd@22 {
|
||||
compatible = "ti,tps6598x";
|
||||
reg = <0x22>;
|
||||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
self-powered;
|
||||
data-role = "dual";
|
||||
power-role = "sink";
|
||||
port {
|
||||
usb_con_hs: endpoint {
|
||||
remote-endpoint = <&typec_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sii9022: bridge-hdmi@39 {
|
||||
compatible = "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_int_pins_default>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
sii9022_in: endpoint {
|
||||
remote-endpoint = <&dpi1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
sii9022_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c02";
|
||||
pagesize = <16>;
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_mcan0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan0_pins_default>;
|
||||
phys = <&can_tc1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
/* Main UART1 may be used by TIFS firmware */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcasp2 {
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcasp2_pins_default>;
|
||||
|
||||
/* MCASP_IIS_MODE */
|
||||
op-mode = <0>;
|
||||
tdm-slots = <2>;
|
||||
|
||||
/* 0: INACTIVE, 1: TX, 2: RX */
|
||||
serial-dir = <
|
||||
0 0 1 2
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
vmmc-supply = <&vcc_3v3_mmc>;
|
||||
vqmmc-supply = <&vddshv5_sdio>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
ti,vbus-divider;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
usb-role-switch;
|
||||
|
||||
port {
|
||||
typec_hs: endpoint {
|
||||
remote-endpoint = <&usb_con_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb1_pins_default>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -59,6 +59,24 @@ epwm_tbclk: clock-controller@4130 {
|
|||
reg = <0x4130 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
audio_refclk0: clock-controller@82e0 {
|
||||
compatible = "ti,am62-audio-refclk";
|
||||
reg = <0x82e0 0x4>;
|
||||
clocks = <&k3_clks 157 0>;
|
||||
assigned-clocks = <&k3_clks 157 0>;
|
||||
assigned-clock-parents = <&k3_clks 157 8>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
audio_refclk1: clock-controller@82e4 {
|
||||
compatible = "ti,am62-audio-refclk";
|
||||
reg = <0x82e4 0x4>;
|
||||
clocks = <&k3_clks 157 10>;
|
||||
assigned-clocks = <&k3_clks 157 10>;
|
||||
assigned-clock-parents = <&k3_clks 157 18>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
dmss: bus@48000000 {
|
||||
|
|
@ -120,8 +138,8 @@ main_pktdma: dma-controller@485c0000 {
|
|||
compatible = "ti,am64-dmss-pktdma";
|
||||
reg = <0x00 0x485c0000 0x00 0x100>,
|
||||
<0x00 0x4a800000 0x00 0x20000>,
|
||||
<0x00 0x4aa00000 0x00 0x40000>,
|
||||
<0x00 0x4b800000 0x00 0x400000>,
|
||||
<0x00 0x4aa00000 0x00 0x20000>,
|
||||
<0x00 0x4b800000 0x00 0x200000>,
|
||||
<0x00 0x485e0000 0x00 0x10000>,
|
||||
<0x00 0x484a0000 0x00 0x2000>,
|
||||
<0x00 0x484c0000 0x00 0x2000>,
|
||||
|
|
@ -216,6 +234,14 @@ k3_reset: reset-controller {
|
|||
};
|
||||
};
|
||||
|
||||
crypto: crypto@40900000 {
|
||||
compatible = "ti,am62-sa3ul";
|
||||
reg = <0x00 0x40900000 0x00 0x1200>;
|
||||
dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
|
||||
<&main_pktdma 0x7507 0>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
};
|
||||
|
||||
secure_proxy_sa3: mailbox@43600000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
|
|
@ -713,7 +739,7 @@ cpsw_port1: port@1 {
|
|||
label = "port1";
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
ti,syscon-efuse = <&wkup_conf 0x200>;
|
||||
ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
|
||||
};
|
||||
|
||||
cpsw_port2: port@2 {
|
||||
|
|
|
|||
330
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
Normal file
330
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
Normal file
|
|
@ -0,0 +1,330 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2023 - 2024 PHYTEC America LLC
|
||||
* Author: Garrett Giordano <ggiordano@phytec.com>
|
||||
*
|
||||
* Product homepage:
|
||||
* https://www.phytec.com/product/phycore-am62a
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
|
||||
/ {
|
||||
model = "PHYTEC phyCORE-AM62Ax";
|
||||
compatible = "phytec,am62a-phycore-som", "ti,am62a7";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cpsw_port1;
|
||||
gpio0 = &main_gpio0;
|
||||
gpio1 = &main_gpio1;
|
||||
i2c0 = &main_i2c0;
|
||||
mmc0 = &sdhci0;
|
||||
rtc0 = &i2c_som_rtc;
|
||||
spi0 = &ospi0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins_default>;
|
||||
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* global cma region */
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x00 0x24000000>;
|
||||
alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c900000 0x00 0x01e00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_5v0_som: regulator-vcc-5v0-som {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_5V0_SOM";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
leds_pins_default: leds-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x034, PIN_OUTPUT, 7) /* (K20) OSPI0_CSN2.GPIO0_13 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */
|
||||
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mdio1_pins_default: main-mdio1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
|
||||
AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc0_pins_default: main-mmc0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */
|
||||
AM62AX_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB7) MMC0_CLK */
|
||||
AM62AX_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */
|
||||
AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */
|
||||
AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */
|
||||
AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */
|
||||
AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */
|
||||
AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */
|
||||
AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */
|
||||
AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_rgmii1_pins_default: main-rgmii1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
|
||||
AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
|
||||
AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
|
||||
AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
|
||||
AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
|
||||
AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
|
||||
AM62AX_IOPAD(0x134, PIN_OUTPUT, 0) /* (Y17) RGMII1_TD0 */
|
||||
AM62AX_IOPAD(0x138, PIN_OUTPUT, 0) /* (V16) RGMII1_TD1 */
|
||||
AM62AX_IOPAD(0x13c, PIN_OUTPUT, 0) /* (Y16) RGMII1_TD2 */
|
||||
AM62AX_IOPAD(0x140, PIN_OUTPUT, 0) /* (AA17) RGMII1_TD3 */
|
||||
AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */
|
||||
AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */
|
||||
AM62AX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */
|
||||
AM62AX_IOPAD(0x038, PIN_OUTPUT, 0) /* (G20) OSPI0_CSn3 */
|
||||
AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */
|
||||
AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */
|
||||
AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */
|
||||
AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */
|
||||
AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */
|
||||
AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */
|
||||
AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */
|
||||
AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
|
||||
AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
|
||||
pmic_irq_pins_default: pmic-irq-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mdio1_pins_default>;
|
||||
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&fss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
pmic@30 {
|
||||
compatible = "ti,tps65219";
|
||||
reg = <0x30>;
|
||||
buck1-supply = <&vcc_5v0_som>;
|
||||
buck2-supply = <&vcc_5v0_som>;
|
||||
buck3-supply = <&vcc_5v0_som>;
|
||||
ldo1-supply = <&vdd_3v3>;
|
||||
ldo2-supply = <&vdd_1v8>;
|
||||
ldo3-supply = <&vcc_5v0_som>;
|
||||
ldo4-supply = <&vcc_5v0_som>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_irq_pins_default>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
ti,power-button;
|
||||
system-power-controller;
|
||||
|
||||
regulators {
|
||||
vdd_3v3: buck1 {
|
||||
regulator-name = "VDD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_1v8: buck2 {
|
||||
regulator-name = "VDD_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_lpddr4: buck3 {
|
||||
regulator-name = "VDD_LPDDR4";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddshv5_sdio: ldo1 {
|
||||
regulator-name = "VDDSHV5_SDIO";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-allow-bypass;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddr_core: ldo2 {
|
||||
regulator-name = "VDDR_CORE";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdda_1v8: ldo3 {
|
||||
regulator-name = "VDDA_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_2v5: ldo4 {
|
||||
regulator-name = "VDD_2V5";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
pagesize = <32>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
i2c_som_rtc: rtc@52 {
|
||||
compatible = "microcrystal,rv3028";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_gpio_intr {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
status = "okay";
|
||||
|
||||
serial_flash: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -6,9 +6,8 @@
|
|||
*/
|
||||
|
||||
&cbass_wakeup {
|
||||
wkup_conf: syscon@43000000 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00 0x43000000 0x00 0x20000>;
|
||||
wkup_conf: bus@43000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00 0x00 0x43000000 0x20000>;
|
||||
|
|
@ -18,6 +17,11 @@ chipid: chipid@14 {
|
|||
reg = <0x14 0x4>;
|
||||
};
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
};
|
||||
|
||||
usb0_phy_ctrl: syscon@4008 {
|
||||
compatible = "ti,am62-usb-phy-ctrl", "syscon";
|
||||
reg = <0x4008 0x4>;
|
||||
|
|
@ -59,7 +63,6 @@ wkup_rtc0: rtc@2b1f0000 {
|
|||
clock-names = "vbus", "osc32k";
|
||||
power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_rti0: watchdog@2b000000 {
|
||||
|
|
|
|||
18
arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts
Normal file
18
arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2023 - 2024 PHYTEC America LLC
|
||||
* Author: Garrett Giordano <ggiordano@phytec.com>
|
||||
*
|
||||
* Product homepage:
|
||||
* https://www.phytec.com/product/phyboard-am62a
|
||||
*/
|
||||
|
||||
#include "k3-am62a7.dtsi"
|
||||
#include "k3-am62a-phycore-som.dtsi"
|
||||
#include "k3-am62x-phyboard-lyra.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "phytec,am62a7-phyboard-lyra-rdk",
|
||||
"phytec,am62a-phycore-som", "ti,am62a7";
|
||||
model = "PHYTEC phyBOARD-Lyra AM62A7";
|
||||
};
|
||||
|
|
@ -40,6 +40,15 @@ reserved-memory {
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* global cma region */
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x00 0x24000000>;
|
||||
alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
|
|
@ -701,8 +710,6 @@ &mcasp1 {
|
|||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&dss {
|
||||
|
|
|
|||
1062
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
Normal file
1062
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Device Tree file for the AM62P MCU domain peripherals
|
||||
* Device Tree file for the MCU domain peripherals shared by AM62P and J722S
|
||||
*
|
||||
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
|
|
@ -11,7 +12,15 @@ mcu_pmx0: pinctrl@4084000 {
|
|||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
pinctrl-single,gpio-range =
|
||||
<&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>;
|
||||
bootph-all;
|
||||
|
||||
mcu_pmx_range: gpio-range {
|
||||
#pinctrl-single,gpio-range-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
mcu_esm: esm@4100000 {
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Device Tree file for the AM62P wakeup domain peripherals
|
||||
* Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S
|
||||
*
|
||||
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
|
|
@ -19,6 +20,11 @@ chipid: chipid@14 {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
};
|
||||
|
||||
usb0_phy_ctrl: syscon@4008 {
|
||||
compatible = "ti,am62-usb-phy-ctrl", "syscon";
|
||||
reg = <0x4008 0x4>;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -116,10 +116,13 @@ cbass_wakeup: bus@b00000 {
|
|||
};
|
||||
};
|
||||
|
||||
#include "k3-am62p-thermal.dtsi"
|
||||
#include "k3-am62p-j722s-common-thermal.dtsi"
|
||||
};
|
||||
|
||||
/* Now include peripherals for each bus segment */
|
||||
#include "k3-am62p-j722s-common-main.dtsi"
|
||||
#include "k3-am62p-j722s-common-mcu.dtsi"
|
||||
#include "k3-am62p-j722s-common-wakeup.dtsi"
|
||||
|
||||
/* Include AM62P specific peripherals */
|
||||
#include "k3-am62p-main.dtsi"
|
||||
#include "k3-am62p-mcu.dtsi"
|
||||
#include "k3-am62p-wakeup.dtsi"
|
||||
|
|
|
|||
|
|
@ -207,7 +207,7 @@ main_mcasp1_pins_default: main-mcasp1-default-pins {
|
|||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
|
||||
AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */
|
||||
AM62PX_IOPAD(0x008c, PIN_INPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */
|
||||
AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */
|
||||
AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */
|
||||
>;
|
||||
};
|
||||
|
|
@ -364,14 +364,9 @@ connector {
|
|||
self-powered;
|
||||
data-role = "dual";
|
||||
power-role = "sink";
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
usb_con_hs: endpoint {
|
||||
remote-endpoint = <&usb0_hs_ep>;
|
||||
};
|
||||
port {
|
||||
usb_con_hs: endpoint {
|
||||
remote-endpoint = <&usb0_hs_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -516,11 +511,8 @@ &usbss1 {
|
|||
|
||||
&usb0 {
|
||||
usb-role-switch;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
port {
|
||||
usb0_hs_ep: endpoint {
|
||||
remote-endpoint = <&usb_con_hs>;
|
||||
};
|
||||
|
|
@ -549,8 +541,6 @@ &mcasp1 {
|
|||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&fss {
|
||||
|
|
|
|||
475
arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
Normal file
475
arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
Normal file
|
|
@ -0,0 +1,475 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
|
||||
* Author: Wadim Egorov <w.egorov@phytec.de>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
mmc1 = &sdhci1;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
};
|
||||
|
||||
can_tc1: can-phy0 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <8000000>;
|
||||
standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
hdmi0: connector-hdmi {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&sii9022_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys_pins_default>;
|
||||
|
||||
key-home {
|
||||
label = "home";
|
||||
linux,code = <KEY_HOME>;
|
||||
gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
key-menu {
|
||||
label = "menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "phyBOARD-Lyra";
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Mic Jack",
|
||||
"Headphone", "Headphone Jack",
|
||||
"Speaker", "External Speaker";
|
||||
simple-audio-card,routing =
|
||||
"MIC3R", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT",
|
||||
"External Speaker", "SPOP",
|
||||
"External Speaker", "SPOM";
|
||||
simple-audio-card,format = "dsp_b";
|
||||
simple-audio-card,bitclock-master = <&sound_master>;
|
||||
simple-audio-card,frame-master = <&sound_master>;
|
||||
simple-audio-card,bitclock-inversion;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&mcasp2>;
|
||||
};
|
||||
|
||||
sound_master: simple-audio-card,codec {
|
||||
sound-dai = <&audio_codec>;
|
||||
clocks = <&audio_refclk1>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
|
||||
|
||||
led-1 {
|
||||
gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc1";
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-vcc-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_mmc: regulator-vcc-3v3-mmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3_MMC";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_sw: regulator-vcc-3v3-sw {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3_SW";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
|
||||
>;
|
||||
};
|
||||
|
||||
gpio_keys_pins_default: gpio-keys-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
|
||||
>;
|
||||
};
|
||||
|
||||
gpio_exp_int_pins_default: gpio-exp-int-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
|
||||
>;
|
||||
};
|
||||
|
||||
hdmi_int_pins_default: hdmi-int-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_dss0_pins_default: main-dss0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
|
||||
AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
|
||||
AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
|
||||
AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
|
||||
AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
|
||||
AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
|
||||
AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
|
||||
AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
|
||||
AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
|
||||
AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
|
||||
AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
|
||||
AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
|
||||
AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
|
||||
AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
|
||||
AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
|
||||
AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
|
||||
AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
|
||||
AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
|
||||
AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
|
||||
AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
|
||||
AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan0_pins_default: main-mcan0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */
|
||||
AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcasp2_pins_default: main-mcasp2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x070, PIN_INPUT, 3) /* (T24) GPMC0_AD13.MCASP2_ACLKX */
|
||||
AM62X_IOPAD(0x06c, PIN_INPUT, 3) /* (T22) GPMC0_AD12.MCASP2_AFSX */
|
||||
AM62X_IOPAD(0x064, PIN_OUTPUT, 3) /* (T25) GPMC0_AD10.MCASP2_AXR2 */
|
||||
AM62X_IOPAD(0x068, PIN_INPUT, 3) /* (R21) GPMC0_AD11.MCASP2_AXR3 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */
|
||||
AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */
|
||||
AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */
|
||||
AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */
|
||||
AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */
|
||||
AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
|
||||
AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_rgmii2_pins_default: main-rgmii2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
|
||||
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
|
||||
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
|
||||
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
|
||||
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
|
||||
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
|
||||
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
|
||||
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
|
||||
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
|
||||
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
|
||||
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
|
||||
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
|
||||
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
|
||||
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
|
||||
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
|
||||
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb1_pins_default: main-usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
user_leds_pins_default: user-leds-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy3>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <3>;
|
||||
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_dss0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dss_ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* VP2: DPI/HDMI Output */
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dpi1_out: endpoint {
|
||||
remote-endpoint = <&sii9022_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
audio_codec: audio-codec@18 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&audio_ext_refclk1_pins_default>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ti,tlv320aic3007";
|
||||
reg = <0x18>;
|
||||
ai3x-micbias-vg = <2>;
|
||||
|
||||
AVDD-supply = <&vcc_3v3_sw>;
|
||||
IOVDD-supply = <&vcc_3v3_sw>;
|
||||
DRVDD-supply = <&vcc_3v3_sw>;
|
||||
DVDD-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
gpio_exp: gpio-expander@21 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_exp_int_pins_default>;
|
||||
compatible = "nxp,pcf8574";
|
||||
reg = <0x21>;
|
||||
interrupt-parent = <&main_gpio1>;
|
||||
interrupts = <49 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-line-names = "", "GPIO1_CAN0_nEN",
|
||||
"GPIO2_LED2", "GPIO3_LVDS_GPIO",
|
||||
"GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN",
|
||||
"GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET";
|
||||
};
|
||||
|
||||
usb-pd@22 {
|
||||
compatible = "ti,tps6598x";
|
||||
reg = <0x22>;
|
||||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
self-powered;
|
||||
data-role = "dual";
|
||||
power-role = "sink";
|
||||
port {
|
||||
usb_con_hs: endpoint {
|
||||
remote-endpoint = <&typec_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sii9022: bridge-hdmi@39 {
|
||||
compatible = "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_int_pins_default>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
sii9022_in: endpoint {
|
||||
remote-endpoint = <&dpi1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
sii9022_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c02";
|
||||
pagesize = <16>;
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_mcan0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan0_pins_default>;
|
||||
phys = <&can_tc1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
/* Main UART1 may be used by TIFS firmware */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcasp2 {
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcasp2_pins_default>;
|
||||
|
||||
/* MCASP_IIS_MODE */
|
||||
op-mode = <0>;
|
||||
tdm-slots = <2>;
|
||||
|
||||
/* 0: INACTIVE, 1: TX, 2: RX */
|
||||
serial-dir = <
|
||||
0 0 1 2
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
vmmc-supply = <&vcc_3v3_mmc>;
|
||||
vqmmc-supply = <&vddshv5_sdio>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
ti,vbus-divider;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
usb-role-switch;
|
||||
|
||||
port {
|
||||
typec_hs: endpoint {
|
||||
remote-endpoint = <&usb_con_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb1_pins_default>;
|
||||
};
|
||||
|
|
@ -48,6 +48,14 @@ ramoops@9ca00000 {
|
|||
pmsg-size = <0x8000>;
|
||||
};
|
||||
|
||||
/* global cma region */
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x00 0x8000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
|
|
@ -128,6 +136,10 @@ hdmi_connector_in: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
&phy_gmii_sel {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
/* First pad number is ALW package and second is AMC package */
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
|
|
@ -156,6 +168,7 @@ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */
|
|||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */
|
||||
AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */
|
||||
|
|
@ -335,15 +348,9 @@ connector {
|
|||
self-powered;
|
||||
data-role = "dual";
|
||||
power-role = "sink";
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
usb_con_hs: endpoint {
|
||||
remote-endpoint = <&usb0_hs_ep>;
|
||||
};
|
||||
port {
|
||||
usb_con_hs: endpoint {
|
||||
remote-endpoint = <&usb0_hs_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -470,12 +477,9 @@ &usbss1 {
|
|||
|
||||
&usb0 {
|
||||
bootph-all;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
usb-role-switch;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
port {
|
||||
usb0_hs_ep: endpoint {
|
||||
remote-endpoint = <&usb_con_hs>;
|
||||
};
|
||||
|
|
@ -504,8 +508,6 @@ &mcasp1 {
|
|||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&dss {
|
||||
|
|
|
|||
|
|
@ -1283,6 +1283,9 @@ pru0_0: pru@34000 {
|
|||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-pru0_0-fw";
|
||||
interrupt-parent = <&icssg0_intc>;
|
||||
interrupts = <16 2 2>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu0_0: rtu@4000 {
|
||||
|
|
@ -1292,6 +1295,9 @@ rtu0_0: rtu@4000 {
|
|||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-rtu0_0-fw";
|
||||
interrupt-parent = <&icssg0_intc>;
|
||||
interrupts = <20 4 4>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru0_0: txpru@a000 {
|
||||
|
|
@ -1310,6 +1316,9 @@ pru0_1: pru@38000 {
|
|||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-pru0_1-fw";
|
||||
interrupt-parent = <&icssg0_intc>;
|
||||
interrupts = <18 3 3>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu0_1: rtu@6000 {
|
||||
|
|
@ -1319,6 +1328,9 @@ rtu0_1: rtu@6000 {
|
|||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-rtu0_1-fw";
|
||||
interrupt-parent = <&icssg0_intc>;
|
||||
interrupts = <22 5 5>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru0_1: txpru@c000 {
|
||||
|
|
@ -1436,6 +1448,9 @@ pru1_0: pru@34000 {
|
|||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-pru1_0-fw";
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <16 2 2>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu1_0: rtu@4000 {
|
||||
|
|
@ -1445,6 +1460,9 @@ rtu1_0: rtu@4000 {
|
|||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-rtu1_0-fw";
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <20 4 4>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru1_0: txpru@a000 {
|
||||
|
|
@ -1463,6 +1481,9 @@ pru1_1: pru@38000 {
|
|||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-pru1_1-fw";
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <18 3 3>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu1_1: rtu@6000 {
|
||||
|
|
@ -1472,6 +1493,9 @@ rtu1_1: rtu@6000 {
|
|||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am64x-rtu1_1-fw";
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <22 5 5>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru1_1: txpru@c000 {
|
||||
|
|
|
|||
|
|
@ -265,6 +265,50 @@ i2c_som_rtc: rtc@52 {
|
|||
interrupts = <70 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
pmic@61 {
|
||||
compatible = "ti,lp8733";
|
||||
reg = <0x61>;
|
||||
|
||||
buck0-in-supply = <&vcc_5v0_som>;
|
||||
buck1-in-supply = <&vcc_5v0_som>;
|
||||
ldo0-in-supply = <&vdd_3v3>;
|
||||
ldo1-in-supply = <&vdd_3v3>;
|
||||
|
||||
regulators {
|
||||
vdd_core: buck0 {
|
||||
regulator-name = "VDD_CORE";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_3v3: buck1 {
|
||||
regulator-name = "VDD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_1v8_ldo0: ldo0 {
|
||||
regulator-name = "VDD_1V8_LDO0";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdda_1v8: ldo1 {
|
||||
regulator-name = "VDDA_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
|
|
@ -296,7 +340,7 @@ &ospi0 {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0 {
|
||||
serial_flash: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
|
||||
* Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
|
||||
* Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
101
arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso
Normal file
101
arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* DT overlay for enabling both ICSSG1 port on AM642 EVM in MII mode
|
||||
*
|
||||
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
&{/} {
|
||||
aliases {
|
||||
ethernet1 = "/icssg1-eth/ethernet-ports/port@1";
|
||||
};
|
||||
|
||||
mdio-mux-2 {
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mdio_mux>;
|
||||
mdio-parent-bus = <&icssg1_mdio>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icssg1_phy2: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
icssg1_mii1_pins_default: icssg1-mii1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00f8, PIN_INPUT, 1) /* (V9) PRG1_PRU0_GPO16.PR1_MII_MT0_CLK */
|
||||
AM64X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y9) PRG1_PRU0_GPO15.PR1_MII0_TXEN */
|
||||
AM64X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA9) PRG1_PRU0_GPO14.PR1_MII0_TXD3 */
|
||||
AM64X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (W9) PRG1_PRU0_GPO13.PR1_MII0_TXD2 */
|
||||
AM64X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (U9) PRG1_PRU0_GPO12.PR1_MII0_TXD1 */
|
||||
AM64X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA8) PRG1_PRU0_GPO11.PR1_MII0_TXD0 */
|
||||
AM64X_IOPAD(0x00c8, PIN_INPUT, 1) /* (Y8) PRG1_PRU0_GPO4.PR1_MII0_RXDV */
|
||||
AM64X_IOPAD(0x00d0, PIN_INPUT, 1) /* (AA7) PRG1_PRU0_GPO6.PR1_MII_MR0_CLK */
|
||||
AM64X_IOPAD(0x00c4, PIN_INPUT, 1) /* (V8) PRG1_PRU0_GPO3.PR1_MII0_RXD3 */
|
||||
AM64X_IOPAD(0x00c0, PIN_INPUT, 1) /* (W8) PRG1_PRU0_GPO2.PR1_MII0_RXD2 */
|
||||
AM64X_IOPAD(0x00cc, PIN_INPUT, 1) /* (V13) PRG1_PRU0_GPO5.PR1_MII0_RXER */
|
||||
AM64X_IOPAD(0x00bc, PIN_INPUT, 1) /* (U8) PRG1_PRU0_GPO1.PR1_MII0_RXD1 */
|
||||
AM64X_IOPAD(0x00b8, PIN_INPUT, 1) /* (Y7) PRG1_PRU0_GPO0.PR1_MII0_RXD0 */
|
||||
AM64X_IOPAD(0x00d8, PIN_INPUT, 1) /* (W13) PRG1_PRU0_GPO8.PR1_MII0_RXLINK */
|
||||
>;
|
||||
};
|
||||
|
||||
icssg1_mii2_pins_default: icssg1-mii2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0148, PIN_INPUT, 1) /* (Y10) PRG1_PRU1_GPO16.PR1_MII_MT1_CLK */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 0) /* (Y11) PRG1_PRU1_GPO15.PR1_MII1_TXEN */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AA11) PRG1_PRU1_GPO14.PR1_MII1_TXD3 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (U10) PRG1_PRU1_GPO13.PR1_MII1_TXD2 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (V10) PRG1_PRU1_GPO12.PR1_MII1_TXD1 */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AA10) PRG1_PRU1_GPO11.PR1_MII1_TXD0 */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 1) /* (W12) PRG1_PRU1_GPO4.PR1_MII1_RXDV */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 1) /* (U11) PRG1_PRU1_GPO6.PR1_MII_MR1_CLK */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 1) /* (Y12) PRG1_PRU1_GPO3.PR1_MII1_RXD3 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 1) /* (AA12) PRG1_PRU1_GPO2.PR1_MII1_RXD2 */
|
||||
AM64X_IOPAD(0x011c, PIN_INPUT, 1) /* (AA13) PRG1_PRU1_GPO5.PR1_MII1_RXER */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 1) /* (V11) PRG1_PRU1_GPO1.PR1_MII1_RXD1 */
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 1) /* (W11) PRG1_PRU1_GPO0.PR1_MII1_RXD0 */
|
||||
AM64X_IOPAD(0x0128, PIN_INPUT, 1) /* (U12) PRG1_PRU1_GPO8.PR1_MII1_RXLINK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-0 = <&rgmii1_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mdio_mux_1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg1_eth {
|
||||
pinctrl-0 = <&icssg1_mii1_pins_default &icssg1_mii2_pins_default>;
|
||||
};
|
||||
|
||||
&icssg1_emac0 {
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
&icssg1_emac1 {
|
||||
status = "okay";
|
||||
phy-handle = <&icssg1_phy2>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
148
arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso
Normal file
148
arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* DT overlay for HSE NAND expansion card on AM642 EVM
|
||||
*
|
||||
* Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
&main_pmx0 {
|
||||
gpmc0_pins_default: gpmc0-pins-default {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */
|
||||
AM64X_IOPAD(0x003c, PIN_INPUT, 0) /* (T20) GPMC0_AD0 */
|
||||
AM64X_IOPAD(0x0040, PIN_INPUT, 0) /* (U21) GPMC0_AD1 */
|
||||
AM64X_IOPAD(0x0064, PIN_INPUT, 0) /* (R16) GPMC0_AD10 */
|
||||
AM64X_IOPAD(0x0068, PIN_INPUT, 0) /* (W20) GPMC0_AD11 */
|
||||
AM64X_IOPAD(0x006c, PIN_INPUT, 0) /* (W21) GPMC0_AD12 */
|
||||
AM64X_IOPAD(0x0070, PIN_INPUT, 0) /* (V18) GPMC0_AD13 */
|
||||
AM64X_IOPAD(0x0074, PIN_INPUT, 0) /* (Y21) GPMC0_AD14 */
|
||||
AM64X_IOPAD(0x0078, PIN_INPUT, 0) /* (Y20) GPMC0_AD15 */
|
||||
AM64X_IOPAD(0x0044, PIN_INPUT, 0) /* (T18) GPMC0_AD2 */
|
||||
AM64X_IOPAD(0x0048, PIN_INPUT, 0) /* (U20) GPMC0_AD3 */
|
||||
AM64X_IOPAD(0x004c, PIN_INPUT, 0) /* (U18) GPMC0_AD4 */
|
||||
AM64X_IOPAD(0x0050, PIN_INPUT, 0) /* (U19) GPMC0_AD5 */
|
||||
AM64X_IOPAD(0x0054, PIN_INPUT, 0) /* (V20) GPMC0_AD6 */
|
||||
AM64X_IOPAD(0x0058, PIN_INPUT, 0) /* (V21) GPMC0_AD7 */
|
||||
AM64X_IOPAD(0x005c, PIN_INPUT, 0) /* (V19) GPMC0_AD8 */
|
||||
AM64X_IOPAD(0x0060, PIN_INPUT, 0) /* (T17) GPMC0_AD9 */
|
||||
AM64X_IOPAD(0x0098, PIN_INPUT_PULLUP, 0) /* (W19) GPMC0_WAIT0 */
|
||||
AM64X_IOPAD(0x009c, PIN_INPUT_PULLUP, 0) /* (Y18) GPMC0_WAIT1 */
|
||||
AM64X_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (R19) GPMC0_CSn0 */
|
||||
AM64X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP, 0) /* (R20) GPMC0_CSn1 */
|
||||
AM64X_IOPAD(0x00b0, PIN_OUTPUT_PULLUP, 0) /* (P19) GPMC0_CSn2 */
|
||||
AM64X_IOPAD(0x00b4, PIN_OUTPUT_PULLUP, 0) /* (R21) GPMC0_CSn3 */
|
||||
AM64X_IOPAD(0x007c, PIN_OUTPUT, 0) /* (R17) GPMC0_CLK */
|
||||
AM64X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (P16) GPMC0_ADVn_ALE */
|
||||
AM64X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (R18) GPMC0_OEn_REn */
|
||||
AM64X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (T21) GPMC0_WEn */
|
||||
AM64X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (P17) GPMC0_BE0n_CLE */
|
||||
AM64X_IOPAD(0x00a0, PIN_OUTPUT_PULLUP, 0) /* (N16) GPMC0_WPn */
|
||||
AM64X_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (N17) GPMC0_DIR */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
gpio0-36 {
|
||||
bootph-all;
|
||||
gpio-hog;
|
||||
gpios = <36 0>;
|
||||
input;
|
||||
line-name = "GPMC0_MUX_DIR";
|
||||
};
|
||||
};
|
||||
|
||||
&elm0 {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpmc0_pins_default>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,am64-nand";
|
||||
reg = <0 0 64>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc0>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
||||
ti,nand-xfer-type = "prefetch-polled";
|
||||
ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
|
||||
ti,elm-id = <&elm0>;
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <40>;
|
||||
gpmc,cs-wr-off-ns = <40>;
|
||||
gpmc,adv-on-ns = <0>;
|
||||
gpmc,adv-rd-off-ns = <25>;
|
||||
gpmc,adv-wr-off-ns = <25>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <20>;
|
||||
gpmc,oe-on-ns = <3>;
|
||||
gpmc,oe-off-ns = <30>;
|
||||
gpmc,access-ns = <30>;
|
||||
gpmc,rd-cycle-ns = <40>;
|
||||
gpmc,wr-cycle-ns = <40>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
bootph-all;
|
||||
label = "NAND.tiboot3";
|
||||
reg = <0x00000000 0x00200000>; /* 2M */
|
||||
};
|
||||
partition@200000 {
|
||||
bootph-all;
|
||||
label = "NAND.tispl";
|
||||
reg = <0x00200000 0x00200000>; /* 2M */
|
||||
};
|
||||
partition@400000 {
|
||||
bootph-all;
|
||||
label = "NAND.tiboot3.backup"; /* 2M */
|
||||
reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
|
||||
};
|
||||
partition@600000 {
|
||||
bootph-all;
|
||||
label = "NAND.u-boot";
|
||||
reg = <0x00600000 0x00400000>; /* 4M */
|
||||
};
|
||||
partition@a00000 {
|
||||
bootph-all;
|
||||
label = "NAND.u-boot-env";
|
||||
reg = <0x00a00000 0x00040000>; /* 256K */
|
||||
};
|
||||
partition@a40000 {
|
||||
bootph-all;
|
||||
label = "NAND.u-boot-env.backup";
|
||||
reg = <0x00a40000 0x00040000>; /* 256K */
|
||||
};
|
||||
partition@a80000 {
|
||||
bootph-all;
|
||||
label = "NAND.file-system";
|
||||
reg = <0x00a80000 0x3f580000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -466,6 +466,12 @@ AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
|
|||
AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
icssg1_iep0_pins_default: icssg1-iep0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
|
|
@ -817,3 +823,12 @@ icssg1_phy1: ethernet-phy@f {
|
|||
rx-internal-delay-ps = <2000>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpmc0 {
|
||||
ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
|
||||
};
|
||||
|
||||
&icssg1_iep0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&icssg1_iep0_pins_default>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -282,7 +282,6 @@ &main_uart3 {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart3_default_pins>;
|
||||
uart-has-rtscts;
|
||||
rs485-rts-active-low;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,87 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* DT overlay for PCIe support (limits USB to 2.0/high-speed)
|
||||
*
|
||||
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
|
||||
* Author: Matt McKee <mmckee@phytec.com>
|
||||
*
|
||||
* Copyright (C) 2024 PHYTEC America, LLC - https://www.phytec.com
|
||||
* Author: Nathan Morrisson <nmorrisson@phytec.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/phy/phy-cadence.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
#include "k3-serdes.h"
|
||||
|
||||
&{/} {
|
||||
pcie_refclk0: pcie-refclk0 {
|
||||
compatible = "gpio-gate-clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_usb_sel_pins_default>;
|
||||
clocks = <&serdes_refclk>;
|
||||
#clock-cells = <0>;
|
||||
enable-gpios = <&main_gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
|
||||
>;
|
||||
};
|
||||
|
||||
pcie_pins_default: pcie-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins_default>;
|
||||
reset-gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_usb_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes0_pcie_usb_link {
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
assigned-clock-parents = <&pcie_refclk0>, <&pcie_refclk0>, <&pcie_refclk0>;
|
||||
};
|
||||
|
||||
&serdes_refclk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Assign pcie_refclk0 to serdes_wiz0 as ext_ref_clk.
|
||||
* This makes sure that the clock generator gets enabled at the right time.
|
||||
*/
|
||||
&serdes_wiz0 {
|
||||
clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&pcie_refclk0>;
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,usb2-only;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
|
@ -190,18 +190,6 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
|
|||
>;
|
||||
};
|
||||
|
||||
pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
|
||||
>;
|
||||
};
|
||||
|
||||
pcie0_pins_default: pcie0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
|
||||
>;
|
||||
};
|
||||
|
||||
user_leds_pins_default: user-leds-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */
|
||||
|
|
|
|||
|
|
@ -430,6 +430,18 @@ exp2: gpio@60 {
|
|||
#gpio-cells = <2>;
|
||||
gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
|
||||
};
|
||||
|
||||
/* SoC power supply temperature */
|
||||
tmp100@48 {
|
||||
compatible = "ti,tmp100";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
/* DDR power supply temperature */
|
||||
tmp100@49 {
|
||||
compatible = "ti,tmp100";
|
||||
reg = <0x49>;
|
||||
};
|
||||
};
|
||||
|
||||
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
|
||||
* Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
|
||||
* Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
|
||||
*/
|
||||
|
||||
#include "k3-am642.dtsi"
|
||||
|
|
|
|||
|
|
@ -1185,6 +1185,9 @@ pru0_0: pru@34000 {
|
|||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru0_0-fw";
|
||||
interrupt-parent = <&icssg0_intc>;
|
||||
interrupts = <16 2 2>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu0_0: rtu@4000 {
|
||||
|
|
@ -1194,6 +1197,9 @@ rtu0_0: rtu@4000 {
|
|||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu0_0-fw";
|
||||
interrupt-parent = <&icssg0_intc>;
|
||||
interrupts = <20 4 4>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru0_0: txpru@a000 {
|
||||
|
|
@ -1212,6 +1218,9 @@ pru0_1: pru@38000 {
|
|||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru0_1-fw";
|
||||
interrupt-parent = <&icssg0_intc>;
|
||||
interrupts = <18 3 3>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu0_1: rtu@6000 {
|
||||
|
|
@ -1221,6 +1230,9 @@ rtu0_1: rtu@6000 {
|
|||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu0_1-fw";
|
||||
interrupt-parent = <&icssg0_intc>;
|
||||
interrupts = <22 5 5>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru0_1: txpru@c000 {
|
||||
|
|
@ -1339,6 +1351,9 @@ pru1_0: pru@34000 {
|
|||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru1_0-fw";
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <16 2 2>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu1_0: rtu@4000 {
|
||||
|
|
@ -1348,6 +1363,9 @@ rtu1_0: rtu@4000 {
|
|||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu1_0-fw";
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <20 4 4>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru1_0: txpru@a000 {
|
||||
|
|
@ -1366,6 +1384,9 @@ pru1_1: pru@38000 {
|
|||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru1_1-fw";
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <18 3 3>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu1_1: rtu@6000 {
|
||||
|
|
@ -1375,6 +1396,9 @@ rtu1_1: rtu@6000 {
|
|||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu1_1-fw";
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <22 5 5>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru1_1: txpru@c000 {
|
||||
|
|
@ -1493,6 +1517,9 @@ pru2_0: pru@34000 {
|
|||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru2_0-fw";
|
||||
interrupt-parent = <&icssg2_intc>;
|
||||
interrupts = <16 2 2>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu2_0: rtu@4000 {
|
||||
|
|
@ -1502,6 +1529,9 @@ rtu2_0: rtu@4000 {
|
|||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu2_0-fw";
|
||||
interrupt-parent = <&icssg2_intc>;
|
||||
interrupts = <20 4 4>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru2_0: txpru@a000 {
|
||||
|
|
@ -1520,6 +1550,9 @@ pru2_1: pru@38000 {
|
|||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru2_1-fw";
|
||||
interrupt-parent = <&icssg2_intc>;
|
||||
interrupts = <18 3 3>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
rtu2_1: rtu@6000 {
|
||||
|
|
@ -1529,6 +1562,9 @@ rtu2_1: rtu@6000 {
|
|||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu2_1-fw";
|
||||
interrupt-parent = <&icssg2_intc>;
|
||||
interrupts = <22 5 5>;
|
||||
interrupt-names = "vring";
|
||||
};
|
||||
|
||||
tx_pru2_1: txpru@c000 {
|
||||
|
|
|
|||
|
|
@ -6,13 +6,17 @@
|
|||
*/
|
||||
|
||||
&cbass_mcu {
|
||||
mcu_conf: scm-conf@40f00000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x40f00000 0x0 0x20000>;
|
||||
mcu_conf: bus@40f00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x40f00000 0x20000>;
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
};
|
||||
|
||||
phy_gmii_sel: phy@4040 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
reg = <0x4040 0x4>;
|
||||
|
|
@ -358,7 +362,7 @@ cpsw_port1: port@1 {
|
|||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||
ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ chosen {
|
|||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
bootph-all;
|
||||
/* 4G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
||||
|
|
|
|||
|
|
@ -414,6 +414,82 @@ &wkup_uart0 {
|
|||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
bootph-all;
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_i2c0_pins_default>;
|
||||
status = "okay";
|
||||
|
||||
lp8733: pmic@60 {
|
||||
compatible = "ti,lp8733";
|
||||
reg = <0x60>;
|
||||
buck0-in-supply = <&vsys_3v3>;
|
||||
buck1-in-supply = <&vsys_3v3>;
|
||||
ldo0-in-supply = <&vsys_3v3>;
|
||||
ldo1-in-supply = <&vsys_3v3>;
|
||||
|
||||
lp8733_regulators: regulators {
|
||||
lp8733_buck0_reg: buck0 {
|
||||
/* FB_B0 -> LP8733-BUCK1 - VDD_MCU_0V85 */
|
||||
regulator-name = "lp8733-buck0";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
lp8733_buck1_reg: buck1 {
|
||||
/* FB_B1 -> LP8733-BUCK2 - VDD_DDR_1V1 */
|
||||
regulator-name = "lp8733-buck1";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
lp8733_ldo0_reg: ldo0 {
|
||||
/* LDO0 -> LP8733-LDO1 - VDA_DLL_0V8 */
|
||||
regulator-name = "lp8733-ldo0";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
lp8733_ldo1_reg: ldo1 {
|
||||
/* LDO1 -> LP8733-LDO2 - VDA_LN_1V8 */
|
||||
regulator-name = "lp8733-ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps62873a: regulator@40 {
|
||||
compatible = "ti,tps62873";
|
||||
reg = <0x40>;
|
||||
bootph-pre-ram;
|
||||
regulator-name = "VDD_CPU_AVS";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
tps62873b: regulator@43 {
|
||||
compatible = "ti,tps62873";
|
||||
reg = <0x43>;
|
||||
regulator-name = "VDD_CORE_0V8";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -11,9 +11,10 @@
|
|||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
bootph-all;
|
||||
/* 16 GB RAM */
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||
<0x08 0x80000000 0x03 0x80000000>;
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000003 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
|
|
@ -130,6 +131,25 @@ rtos_ipc_memory_region: ipc-memories@a8000000 {
|
|||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
|
||||
J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
|
||||
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
|
||||
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
|
||||
J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
|
||||
J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
|
||||
J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
|
||||
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
|
||||
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
|
||||
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
|
||||
J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx2 {
|
||||
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
|
|
@ -152,6 +172,68 @@ eeprom@51 {
|
|||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
bootph-all;
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x680000 0x40000>;
|
||||
};
|
||||
|
||||
partition@740000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x740000 0x40000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
bootph-pre-ram;
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
|
|
|||
|
|
@ -35,8 +35,8 @@ memory@80000000 {
|
|||
device_type = "memory";
|
||||
bootph-all;
|
||||
/* 32G RAM */
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||
<0x08 0x80000000 0x07 0x80000000>;
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000007 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
|
|
@ -814,6 +814,27 @@ ldoa4: ldo4 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps62873a: regulator@40 {
|
||||
compatible = "ti,tps62873";
|
||||
reg = <0x40>;
|
||||
bootph-pre-ram;
|
||||
regulator-name = "VDD_CPU_AVS";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
tps62873b: regulator@43 {
|
||||
compatible = "ti,tps62873";
|
||||
reg = <0x43>;
|
||||
regulator-name = "VDD_CORE_0V8";
|
||||
regulator-min-microvolt = <760000>;
|
||||
regulator-max-microvolt = <840000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
|
|
@ -1203,3 +1224,65 @@ partition@3fc0000 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
|
||||
<J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_USB>,
|
||||
<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
|
||||
<J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>;
|
||||
};
|
||||
|
||||
&serdes_wiz0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
status = "okay";
|
||||
|
||||
serdes0_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <3>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_wiz1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes1 {
|
||||
status = "okay";
|
||||
|
||||
serdes1_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <4>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, <&serdes_wiz1 3>, <&serdes_wiz1 4>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "okay";
|
||||
reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes1_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
status = "okay";
|
||||
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <2>;
|
||||
};
|
||||
|
||||
&pcie3_rc {
|
||||
status = "okay";
|
||||
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
};
|
||||
|
|
|
|||
19
arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso
Normal file
19
arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2023 PHYTEC America, LLC
|
||||
* Author: Garrett Giordano <ggiordano@phytec.com>
|
||||
*
|
||||
* Copyright (C) 2024 PHYTEC America, LLC
|
||||
* Author: Nathan Morrisson <nmorrisson@phytec.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&cpsw3g_phy1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
status = "disabled";
|
||||
};
|
||||
15
arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso
Normal file
15
arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2023 PHYTEC America, LLC
|
||||
* Author: Garrett Giordano <ggiordano@phytec.com>
|
||||
*
|
||||
* Copyright (C) 2024 PHYTEC America, LLC
|
||||
* Author: Nathan Morrisson <nmorrisson@phytec.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&i2c_som_rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
15
arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso
Normal file
15
arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2023 PHYTEC America, LLC
|
||||
* Author: Garrett Giordano <ggiordano@phytec.com>
|
||||
*
|
||||
* Copyright (C) 2024 PHYTEC America, LLC
|
||||
* Author: Nathan Morrisson <nmorrisson@phytec.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&serial_flash {
|
||||
status = "disabled";
|
||||
};
|
||||
15
arch/arm64/boot/dts/ti/k3-am6xx-phycore-qspi-nor.dtso
Normal file
15
arch/arm64/boot/dts/ti/k3-am6xx-phycore-qspi-nor.dtso
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 PHYTEC America LLC
|
||||
* Author: Nathan Morrisson <nmorrisson@phytec.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
&serial_flash {
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
|
|
@ -164,12 +164,16 @@ mcu_timer9: timer@40490000 {
|
|||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
mcu_conf: syscon@40f00000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x00 0x40f00000 0x00 0x20000>;
|
||||
mcu_conf: bus@40f00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00 0x00 0x40f00000 0x20000>;
|
||||
ranges = <0x0 0x0 0x40f00000 0x20000>;
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
};
|
||||
|
||||
phy_gmii_sel: phy@4040 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
|
|
@ -420,7 +424,7 @@ cpsw_port1: port@1 {
|
|||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||
ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,9 +12,10 @@
|
|||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
bootph-all;
|
||||
/* 4G RAM */
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||
<0x08 0x80000000 0x00 0x80000000>;
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,164 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Infotainment Expansion Board for j721e-evm
|
||||
* User Guide: <https://www.ti.com/lit/ug/spruit0a/spruit0a.pdf>
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
&{/} {
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
type = "a";
|
||||
ddc-i2c-bus = <&main_i2c1>;
|
||||
digital;
|
||||
/* P12 - HDMI_HPD */
|
||||
hpd-gpios = <&exp6 10 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&tfp410_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dvi-bridge {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "ti,tfp410";
|
||||
/* P10 - HDMI_PDn */
|
||||
powerdown-gpios = <&exp6 8 GPIO_ACTIVE_LOW>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tfp410_in: endpoint {
|
||||
remote-endpoint = <&dpi_out0>;
|
||||
pclk-sample = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
tfp410_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_i2c1_exp6_pins_default: main-i2c1-exp6-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x264, PIN_INPUT, 7) /* (T29) MMC2_DAT2.GPIO1_24 */
|
||||
>;
|
||||
};
|
||||
|
||||
dss_vout0_pins_default: dss-vout0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
|
||||
J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
|
||||
J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
|
||||
J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
|
||||
J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
|
||||
J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
|
||||
J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
|
||||
J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
|
||||
J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
|
||||
J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
|
||||
J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
|
||||
J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
|
||||
J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
|
||||
J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
|
||||
J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
|
||||
J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
|
||||
J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
|
||||
J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
|
||||
J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
|
||||
J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
|
||||
J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
|
||||
J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
|
||||
J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
|
||||
J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
|
||||
J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
|
||||
J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
|
||||
J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
|
||||
J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&exp1 {
|
||||
p14-hog {
|
||||
/* P14 - VINOUT_MUX_SEL0 */
|
||||
gpio-hog;
|
||||
gpios = <12 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "VINOUT_MUX_SEL0";
|
||||
};
|
||||
|
||||
p15-hog {
|
||||
/* P15 - VINOUT_MUX_SEL1 */
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "VINOUT_MUX_SEL1";
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
/* i2c1 is used for DVI DDC, so we need to use 100kHz */
|
||||
clock-frequency = <100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
exp6: gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_exp6_pins_default>;
|
||||
interrupt-parent = <&main_gpio1>;
|
||||
interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
p11-hog {
|
||||
/* P11 - HDMI_DDC_OE */
|
||||
gpio-hog;
|
||||
gpios = <9 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "HDMI_DDC_OE";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_vout0_pins_default>;
|
||||
};
|
||||
|
||||
&dss_ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dpi_out0: endpoint {
|
||||
remote-endpoint = <&tfp410_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -34,13 +34,17 @@ k3_reset: reset-controller {
|
|||
};
|
||||
};
|
||||
|
||||
mcu_conf: syscon@40f00000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x40f00000 0x0 0x20000>;
|
||||
mcu_conf: bus@40f00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x40f00000 0x20000>;
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
};
|
||||
|
||||
phy_gmii_sel: phy@4040 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
reg = <0x4040 0x4>;
|
||||
|
|
@ -546,7 +550,7 @@ cpsw_port1: port@1 {
|
|||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||
ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ chosen {
|
|||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
bootph-all;
|
||||
/* 4G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
||||
|
|
@ -210,6 +211,42 @@ vdd_sd_dv_alt: gpio-regulator-tps659411 {
|
|||
<3300000 0x1>;
|
||||
};
|
||||
|
||||
transceiver1: can-phy1 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
|
||||
standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
transceiver2: can-phy2 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan0_gpio_pins_default>;
|
||||
standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
transceiver3: can-phy3 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan5_gpio_pins_default>;
|
||||
standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
transceiver4: can-phy4 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan9_gpio_pins_default>;
|
||||
standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
dp_pwr_3v3: fixedregulator-dp-prw {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dp-pwr";
|
||||
|
|
@ -367,6 +404,45 @@ J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */
|
|||
>;
|
||||
};
|
||||
|
||||
main_mcan0_pins_default: main-mcan0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
|
||||
J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan5_pins_default: main-mcan5-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */
|
||||
J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan9_pins_default: main-mcan9-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */
|
||||
J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
|
||||
>;
|
||||
};
|
||||
|
||||
dp0_pins_default: dp0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
|
||||
|
|
@ -555,6 +631,19 @@ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
|
|||
>;
|
||||
};
|
||||
|
||||
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
|
||||
J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */
|
||||
>;
|
||||
};
|
||||
|
||||
/* Reset for M.2 M Key slot on PCIe1 */
|
||||
mkey_reset_pins_default: mkey-reset-pns-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
|
|
@ -1108,6 +1197,34 @@ &pcie1_rc {
|
|||
num-lanes = <2>;
|
||||
};
|
||||
|
||||
&mcu_mcan0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_mcan0_pins_default>;
|
||||
phys = <&transceiver1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_mcan0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan0_pins_default>;
|
||||
phys = <&transceiver2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_mcan5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan5_pins_default>;
|
||||
phys = <&transceiver3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_mcan9 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan9_pins_default>;
|
||||
phys = <&transceiver4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_wrapper {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
bootph-all;
|
||||
/* 4G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
||||
|
|
|
|||
|
|
@ -139,13 +139,17 @@ wkup_gpio_intr: interrupt-controller@42200000 {
|
|||
ti,interrupt-ranges = <16 960 16>;
|
||||
};
|
||||
|
||||
mcu_conf: syscon@40f00000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x40f00000 0x0 0x20000>;
|
||||
mcu_conf: bus@40f00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x40f00000 0x20000>;
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
};
|
||||
|
||||
phy_gmii_sel: phy@4040 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
reg = <0x4040 0x4>;
|
||||
|
|
@ -544,7 +548,7 @@ cpsw_port1: port@1 {
|
|||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||
ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -13,9 +13,10 @@
|
|||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
bootph-all;
|
||||
/* 16 GB RAM */
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||
<0x08 0x80000000 0x03 0x80000000>;
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000003 0x80000000>;
|
||||
};
|
||||
|
||||
/* Reserving memory regions still pending */
|
||||
|
|
|
|||
|
|
@ -9,7 +9,9 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include "k3-j722s.dtsi"
|
||||
#include "k3-serdes.h"
|
||||
|
||||
/ {
|
||||
compatible = "ti,j722s-evm", "ti,j722s";
|
||||
|
|
@ -105,6 +107,15 @@ vdd_sd_dv: regulator-TLV71033 {
|
|||
<3300000 0x1>;
|
||||
};
|
||||
|
||||
vsys_io_3v3: regulator-vsys-io-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_io_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_io_1v8: regulator-vsys-io-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_io_1v8";
|
||||
|
|
@ -122,6 +133,35 @@ vsys_io_1v2: regulator-vsys-io-1v2 {
|
|||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
codec_audio: sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "J722S-EVM";
|
||||
simple-audio-card,widgets =
|
||||
"Headphone", "Headphone Jack",
|
||||
"Line", "Line In",
|
||||
"Microphone", "Microphone Jack";
|
||||
simple-audio-card,routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT",
|
||||
"LINE1L", "Line In",
|
||||
"LINE1R", "Line In",
|
||||
"MIC3R", "Microphone Jack",
|
||||
"Microphone Jack", "Mic Bias";
|
||||
simple-audio-card,format = "dsp_b";
|
||||
simple-audio-card,bitclock-master = <&sound_master>;
|
||||
simple-audio-card,frame-master = <&sound_master>;
|
||||
simple-audio-card,bitclock-inversion;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&mcasp1>;
|
||||
};
|
||||
|
||||
sound_master: simple-audio-card,codec {
|
||||
sound-dai = <&tlv320aic3106>;
|
||||
clocks = <&audio_refclk1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -202,6 +242,27 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
|
|||
J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb1_pins_default: main-usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcasp1_pins_default: main-mcasp1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (P27) GPMC0_BE0n_CLE.MCASP1_ACLKX */
|
||||
J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (V21) GPMC0_WAIT0.MCASP1_AFSX */
|
||||
J722S_IOPAD(0x008c, PIN_OUTPUT, 2) /* (N23) GPMC0_WEn.MCASP1_AXR0 */
|
||||
J722S_IOPAD(0x0084, PIN_INPUT, 2) /* (N21) GPMC0_ADVn_ALE.MCASP1_AXR2 */
|
||||
>;
|
||||
};
|
||||
|
||||
audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
|
|
@ -277,6 +338,12 @@ &wkup_i2c0 {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
/* Configure AUDIO_EXT_REFCLK1 pin as output */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&audio_ext_refclk1_pins_default>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
|
|
@ -301,6 +368,48 @@ exp1: gpio@23 {
|
|||
"PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
|
||||
"ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
|
||||
"PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
|
||||
|
||||
p05-hog {
|
||||
/* P05 - USB2.0_MUX_SEL */
|
||||
gpio-hog;
|
||||
gpios = <5 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
p01_hog: p01-hog {
|
||||
/* P01 - TRC_MUX_SEL */
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "TRC_MUX_SEL";
|
||||
};
|
||||
|
||||
p02_hog: p02-hog {
|
||||
/* P02 - MCASP1_FET_SEL */
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "MCASP1_FET_SEL";
|
||||
};
|
||||
|
||||
p13_hog: p13-hog {
|
||||
/* P13 - GPIO_AUD_RSTn */
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "GPIO_AUD_RSTn";
|
||||
};
|
||||
};
|
||||
|
||||
tlv320aic3106: audio-codec@1b {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x1b>;
|
||||
ai3x-micbias-vg = <1>; /* 2.0V */
|
||||
AVDD-supply = <&vsys_io_3v3>;
|
||||
IOVDD-supply = <&vsys_io_3v3>;
|
||||
DRVDD-supply = <&vsys_io_3v3>;
|
||||
DVDD-supply = <&vsys_io_1v8>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -384,3 +493,76 @@ &sdhci1 {
|
|||
status = "okay";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <J722S_SERDES0_LANE0_USB>,
|
||||
<J722S_SERDES1_LANE0_PCIE0_LANE0>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
status = "okay";
|
||||
serdes0_usb_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USB3>;
|
||||
resets = <&serdes_wiz0 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes1 {
|
||||
status = "okay";
|
||||
serdes1_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz1 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes1_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "otg";
|
||||
usb-role-switch;
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb1_pins_default>;
|
||||
ti,vbus-divider;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
maximum-speed = "super-speed";
|
||||
phys = <&serdes0_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
||||
&mcasp1 {
|
||||
status = "okay";
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcasp1_pins_default>;
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
1 0 2 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
};
|
||||
|
|
|
|||
217
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
Normal file
217
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
Normal file
|
|
@ -0,0 +1,217 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Device Tree file for the J722S MAIN domain peripherals
|
||||
*
|
||||
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/phy/phy-cadence.h>
|
||||
#include <dt-bindings/phy/phy-ti.h>
|
||||
|
||||
/ {
|
||||
serdes_refclk: clk-0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
serdes_wiz0: phy@f000000 {
|
||||
compatible = "ti,am64-wiz-10g";
|
||||
ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
num-lanes = <1>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
assigned-clocks = <&k3_clks 279 1>;
|
||||
assigned-clock-parents = <&k3_clks 279 5>;
|
||||
|
||||
serdes0: serdes@f000000 {
|
||||
compatible = "ti,j721e-serdes-10g";
|
||||
reg = <0x0f000000 0x00010000>;
|
||||
reg-names = "torrent_phy";
|
||||
resets = <&serdes_wiz0 0>;
|
||||
reset-names = "torrent_reset";
|
||||
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
|
||||
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
|
||||
clock-names = "refclk", "phy_en_refclk";
|
||||
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
|
||||
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
|
||||
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
|
||||
assigned-clock-parents = <&k3_clks 279 1>,
|
||||
<&k3_clks 279 1>,
|
||||
<&k3_clks 279 1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
status = "disabled"; /* Needs lane config */
|
||||
};
|
||||
};
|
||||
|
||||
serdes_wiz1: phy@f010000 {
|
||||
compatible = "ti,am64-wiz-10g";
|
||||
ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
num-lanes = <1>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
assigned-clocks = <&k3_clks 280 1>;
|
||||
assigned-clock-parents = <&k3_clks 280 5>;
|
||||
|
||||
serdes1: serdes@f010000 {
|
||||
compatible = "ti,j721e-serdes-10g";
|
||||
reg = <0x0f010000 0x00010000>;
|
||||
reg-names = "torrent_phy";
|
||||
resets = <&serdes_wiz1 0>;
|
||||
reset-names = "torrent_reset";
|
||||
clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
|
||||
<&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
|
||||
clock-names = "refclk", "phy_en_refclk";
|
||||
assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
|
||||
<&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
|
||||
<&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
|
||||
assigned-clock-parents = <&k3_clks 280 1>,
|
||||
<&k3_clks 280 1>,
|
||||
<&k3_clks 280 1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
status = "disabled"; /* Needs lane config */
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_rc: pcie@f102000 {
|
||||
compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
|
||||
reg = <0x00 0x0f102000 0x00 0x1000>,
|
||||
<0x00 0x0f100000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x68000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
|
||||
<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <1>;
|
||||
power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
|
||||
clock-names = "fck", "pcie_refclk";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb010>;
|
||||
cdns,no-bar-match-nbits = <64>;
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbss1: usb@f920000 {
|
||||
compatible = "ti,j721e-usb";
|
||||
reg = <0x00 0x0f920000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
|
||||
clock-names = "ref", "lpm";
|
||||
assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
|
||||
assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
usb1: usb@31200000{
|
||||
compatible = "cdns,usb3";
|
||||
reg = <0x00 0x31200000 0x00 0x10000>,
|
||||
<0x00 0x31210000 0x00 0x10000>,
|
||||
<0x00 0x31220000 0x00 0x10000>;
|
||||
reg-names = "otg",
|
||||
"xhci",
|
||||
"dev";
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
||||
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
||||
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
|
||||
interrupt-names = "host",
|
||||
"peripheral",
|
||||
"otg";
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_conf {
|
||||
serdes_ln_ctrl: mux-controller@4080 {
|
||||
compatible = "reg-mux";
|
||||
reg = <0x4080 0x14>;
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
|
||||
<0x10 0x3>; /* SERDES1 lane0 select */
|
||||
};
|
||||
|
||||
audio_refclk1: clock@82e4 {
|
||||
compatible = "ti,am62-audio-refclk";
|
||||
reg = <0x82e4 0x4>;
|
||||
clocks = <&k3_clks 157 18>;
|
||||
assigned-clocks = <&k3_clks 157 18>;
|
||||
assigned-clock-parents = <&k3_clks 157 33>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_conf {
|
||||
pcie0_ctrl: pcie0-ctrl@4070 {
|
||||
compatible = "ti,j784s4-pcie-ctrl", "syscon";
|
||||
reg = <0x4070 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
&oc_sram {
|
||||
reg = <0x00 0x70000000 0x00 0x40000>;
|
||||
ranges = <0x00 0x00 0x70000000 0x40000>;
|
||||
};
|
||||
|
||||
&inta_main_dmss {
|
||||
ti,interrupt-ranges = <7 71 21>;
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
pinctrl-single,gpio-range =
|
||||
<&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 33 55 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
|
||||
|
||||
main_pmx0_range: gpio-range {
|
||||
#pinctrl-single,gpio-range-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
|
||||
<&main_pmx0 70 72 17>;
|
||||
ti,ngpio = <87>;
|
||||
};
|
||||
|
||||
&main_gpio1 {
|
||||
gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
|
||||
<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
|
||||
ti,ngpio = <73>;
|
||||
};
|
||||
|
|
@ -10,11 +10,133 @@
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
#include "k3-am62p5.dtsi"
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 J722S SoC";
|
||||
compatible = "ti,j722s";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
clocks = <&k3_clks 135 0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
clocks = <&k3_clks 136 0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x002>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
clocks = <&k3_clks 137 0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x003>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
clocks = <&k3_clks 138 0>;
|
||||
};
|
||||
};
|
||||
|
||||
l2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a53_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@f0000 {
|
||||
compatible = "simple-bus";
|
||||
|
|
@ -74,16 +196,39 @@ cbass_main: bus@f0000 {
|
|||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
|
||||
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
|
||||
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
|
||||
|
||||
cbass_mcu: bus@4000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
|
||||
<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
|
||||
<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
|
||||
<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
|
||||
<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
cbass_wakeup: bus@b00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
|
||||
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
|
||||
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
|
||||
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
#include "k3-am62p-j722s-common-thermal.dtsi"
|
||||
};
|
||||
|
||||
/* Main domain overrides */
|
||||
/* Include peripherals shared with AM62P */
|
||||
#include "k3-am62p-j722s-common-main.dtsi"
|
||||
#include "k3-am62p-j722s-common-mcu.dtsi"
|
||||
#include "k3-am62p-j722s-common-wakeup.dtsi"
|
||||
|
||||
&inta_main_dmss {
|
||||
ti,interrupt-ranges = <7 71 21>;
|
||||
};
|
||||
|
||||
&oc_sram {
|
||||
reg = <0x00 0x70000000 0x00 0x40000>;
|
||||
ranges = <0x00 0x00 0x70000000 0x40000>;
|
||||
};
|
||||
/* Include J722S specific peripherals */
|
||||
#include "k3-j722s-main.dtsi"
|
||||
|
|
|
|||
79
arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
Normal file
79
arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* DT Overlay for enabling PCIE0 and PCIE1 instances in Endpoint Configuration
|
||||
* on J784S4 EVM.
|
||||
*
|
||||
* J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
/*
|
||||
* Since Root Complex and Endpoint modes are mutually exclusive
|
||||
* disable Root Complex mode.
|
||||
*/
|
||||
&pcie0_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
||||
pcie0_ep: pcie-ep@2900000 {
|
||||
compatible = "ti,j784s4-pcie-ep";
|
||||
reg = <0x00 0x02900000 0x00 0x1000>,
|
||||
<0x00 0x02907000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x10000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <4>;
|
||||
power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 332 0>;
|
||||
clock-names = "fck";
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
phys = <&serdes1_pcie0_link>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
|
||||
pcie1_ep: pcie-ep@2910000 {
|
||||
compatible = "ti,j784s4-pcie-ep";
|
||||
reg = <0x00 0x02910000 0x00 0x1000>,
|
||||
<0x00 0x02917000 0x00 0x400>,
|
||||
<0x00 0x0d800000 0x00 0x00800000>,
|
||||
<0x00 0x18000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 333 0>;
|
||||
clock-names = "fck";
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
phys = <&serdes0_pcie1_link>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
};
|
||||
147
arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
Normal file
147
arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
Normal file
|
|
@ -0,0 +1,147 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
|
||||
/**
|
||||
* DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
|
||||
* J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
|
||||
* board.
|
||||
*
|
||||
* Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf
|
||||
*
|
||||
* Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy-cadence.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
#include "k3-serdes.h"
|
||||
|
||||
&{/} {
|
||||
aliases {
|
||||
ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
|
||||
ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
|
||||
ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
|
||||
ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
|
||||
ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
|
||||
};
|
||||
};
|
||||
|
||||
&main_cpsw0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_cpsw0_port5 {
|
||||
phy-handle = <&cpsw9g_phy1>;
|
||||
phy-mode = "qsgmii";
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
|
||||
phy-names = "mac", "serdes";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_cpsw0_port6 {
|
||||
phy-handle = <&cpsw9g_phy2>;
|
||||
phy-mode = "qsgmii";
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
|
||||
phy-names = "mac", "serdes";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_cpsw0_port7 {
|
||||
phy-handle = <&cpsw9g_phy0>;
|
||||
phy-mode = "qsgmii";
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
|
||||
phy-names = "mac", "serdes";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_cpsw0_port8 {
|
||||
phy-handle = <&cpsw9g_phy3>;
|
||||
phy-mode = "qsgmii";
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
|
||||
phy-names = "mac", "serdes";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_cpsw0_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio0_default_pins>;
|
||||
bus_freq = <1000000>;
|
||||
reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
|
||||
reset-post-delay-us = <120000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
cpsw9g_phy0: ethernet-phy@16 {
|
||||
reg = <16>;
|
||||
};
|
||||
cpsw9g_phy1: ethernet-phy@17 {
|
||||
reg = <17>;
|
||||
};
|
||||
cpsw9g_phy2: ethernet-phy@18 {
|
||||
reg = <18>;
|
||||
};
|
||||
cpsw9g_phy3: ethernet-phy@19 {
|
||||
reg = <19>;
|
||||
};
|
||||
};
|
||||
|
||||
&exp2 {
|
||||
/* Power-up ENET1 EXPANDER PHY. */
|
||||
qsgmii-line-hog {
|
||||
gpio-hog;
|
||||
gpios = <16 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
};
|
||||
|
||||
/* Toggle MUX2 for MDIO lines */
|
||||
mux-sel-hog {
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
mdio0_default_pins: mdio0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */
|
||||
J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
|
||||
<J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
|
||||
<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
|
||||
<J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
|
||||
<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
|
||||
<J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
|
||||
};
|
||||
|
||||
&serdes_wiz2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
serdes2_qsgmii_link: phy@0 {
|
||||
reg = <2>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_QSGMII>;
|
||||
resets = <&serdes_wiz2 3>;
|
||||
};
|
||||
};
|
||||
81
arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
Normal file
81
arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
|
||||
/**
|
||||
* DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
|
||||
* and ENET-2 Expansion slots of J784S4 EVM.
|
||||
*
|
||||
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy-cadence.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
#include "k3-serdes.h"
|
||||
|
||||
&{/} {
|
||||
aliases {
|
||||
ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
|
||||
ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
|
||||
ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
|
||||
};
|
||||
};
|
||||
|
||||
&main_cpsw0 {
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_cpsw0_port1 {
|
||||
phy-mode = "usxgmii";
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
|
||||
phy-names = "mac", "serdes";
|
||||
status = "okay";
|
||||
fixed-link {
|
||||
speed = <5000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&main_cpsw0_port2 {
|
||||
phy-mode = "usxgmii";
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
|
||||
phy-names = "mac", "serdes";
|
||||
status = "okay";
|
||||
fixed-link {
|
||||
speed = <5000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_wiz2 {
|
||||
assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
serdes2_usxgmii_link: phy@2 {
|
||||
reg = <2>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USXGMII>;
|
||||
resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
|
||||
<J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
|
||||
<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
|
||||
<J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
|
||||
<J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
|
||||
<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
|
||||
};
|
||||
|
|
@ -27,14 +27,16 @@ aliases {
|
|||
mmc1 = &main_sdhci1;
|
||||
i2c0 = &wkup_i2c0;
|
||||
i2c3 = &main_i2c0;
|
||||
ethernet0 = &mcu_cpsw_port1;
|
||||
ethernet1 = &main_cpsw1_port1;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
bootph-all;
|
||||
/* 32G RAM */
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||
<0x08 0x80000000 0x07 0x80000000>;
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000007 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
|
|
@ -272,6 +274,59 @@ dp0_connector_in: endpoint {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
transceiver0: can-phy0 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
|
||||
standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
transceiver1: can-phy1 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
|
||||
standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
transceiver2: can-phy2 {
|
||||
/* standby pin has been grounded by default */
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
};
|
||||
|
||||
transceiver3: can-phy3 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
|
||||
mux-states = <&mux1 1>;
|
||||
};
|
||||
|
||||
mux1: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-state-cells = <1>;
|
||||
mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>;
|
||||
idle-state = <1>;
|
||||
};
|
||||
|
||||
codec_audio: sound {
|
||||
compatible = "ti,j7200-cpb-audio";
|
||||
model = "j784s4-cpb";
|
||||
|
||||
ti,cpb-mcasp = <&mcasp0>;
|
||||
ti,cpb-codec = <&pcm3168a_1>;
|
||||
|
||||
clocks = <&k3_clks 265 0>, <&k3_clks 265 1>,
|
||||
<&k3_clks 157 34>, <&k3_clks 157 63>;
|
||||
clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000",
|
||||
"cpb-codec-scki", "cpb-codec-scki-48000";
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
|
|
@ -280,6 +335,30 @@ &wkup_gpio0 {
|
|||
|
||||
&main_pmx0 {
|
||||
bootph-all;
|
||||
main_cpsw2g_default_pins: main-cpsw2g-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
|
||||
J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
|
||||
J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
|
||||
J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
|
||||
J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
|
||||
J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
|
||||
J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
|
||||
J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
|
||||
J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
|
||||
J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
|
||||
J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
|
||||
J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
|
||||
J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart8_pins_default: main-uart8-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
|
|
@ -336,6 +415,49 @@ J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
|
|||
J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan4_pins_default: main-mcan4-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */
|
||||
J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan16_pins_default: main-mcan16-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */
|
||||
J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usbss0_pins_default: main-usbss0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c3_pins_default: main-i2c3-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */
|
||||
J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcasp0_pins_default: main-mcasp0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */
|
||||
J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */
|
||||
J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */
|
||||
J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */
|
||||
>;
|
||||
};
|
||||
|
||||
audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx2 {
|
||||
|
|
@ -415,6 +537,32 @@ J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */
|
|||
J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */
|
||||
J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */
|
||||
J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx1 {
|
||||
|
|
@ -579,6 +727,27 @@ ldoa4: ldo4 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps62873a: regulator@40 {
|
||||
compatible = "ti,tps62873";
|
||||
reg = <0x40>;
|
||||
bootph-pre-ram;
|
||||
regulator-name = "VDD_CPU_AVS";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1330000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
tps62873b: regulator@43 {
|
||||
compatible = "ti,tps62873";
|
||||
reg = <0x43>;
|
||||
regulator-name = "VDD_CORE_0V8";
|
||||
regulator-min-microvolt = <760000>;
|
||||
regulator-max-microvolt = <840000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
|
|
@ -748,6 +917,14 @@ exp1: gpio@20 {
|
|||
"PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#",
|
||||
"PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3",
|
||||
"AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ";
|
||||
|
||||
p12-hog {
|
||||
/* P12 - AUDIO_MUX_SEL */
|
||||
gpio-hog;
|
||||
gpios = <12 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "AUDIO_MUX_SEL";
|
||||
};
|
||||
};
|
||||
|
||||
exp2: gpio@22 {
|
||||
|
|
@ -763,6 +940,22 @@ exp2: gpio@22 {
|
|||
"CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ",
|
||||
"ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ",
|
||||
"USER_INPUT1", "USER_LED1", "USER_LED2";
|
||||
|
||||
p13-hog {
|
||||
/* P13 - CANUART_MUX_SEL0 */
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "CANUART_MUX_SEL0";
|
||||
};
|
||||
|
||||
p15-hog {
|
||||
/* P15 - CANUART_MUX1_SEL1 */
|
||||
gpio-hog;
|
||||
gpios = <15 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "CANUART_MUX1_SEL1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -832,6 +1025,31 @@ &mcu_cpsw_port1 {
|
|||
phy-handle = <&mcu_phy0>;
|
||||
};
|
||||
|
||||
&main_cpsw1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_cpsw2g_default_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_cpsw1_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_cpsw2g_mdio_default_pins>;
|
||||
status = "okay";
|
||||
|
||||
main_cpsw1_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
||||
&main_cpsw1_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&main_cpsw1_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
|
@ -1041,6 +1259,40 @@ &dss {
|
|||
<&k3_clks 218 22>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
status = "okay";
|
||||
|
||||
serdes0_usb_link: phy@3 {
|
||||
reg = <3>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USB3>;
|
||||
resets = <&serdes_wiz0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_wiz0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_serdes_mux {
|
||||
idle-states = <0>; /* USB0 to SERDES lane 3 */
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "super-speed";
|
||||
phys = <&serdes0_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
||||
&serdes_wiz4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1105,3 +1357,130 @@ dp0_out: endpoint {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_mcan0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_mcan0_pins_default>;
|
||||
phys = <&transceiver0>;
|
||||
};
|
||||
|
||||
&mcu_mcan1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_mcan1_pins_default>;
|
||||
phys = <&transceiver1>;
|
||||
};
|
||||
|
||||
&main_mcan16 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan16_pins_default>;
|
||||
phys = <&transceiver2>;
|
||||
};
|
||||
|
||||
&main_mcan4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan4_pins_default>;
|
||||
phys = <&transceiver3>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
status = "okay";
|
||||
|
||||
serdes0_pcie1_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <4>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>,
|
||||
<&serdes_wiz0 3>, <&serdes_wiz0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_wiz0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
status = "okay";
|
||||
num-lanes = <2>;
|
||||
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie1_link>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
|
||||
&serdes1 {
|
||||
status = "okay";
|
||||
|
||||
serdes1_pcie0_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_wiz1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "okay";
|
||||
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes1_pcie0_link>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
/* Confiure AUDIO_EXT_REFCLK1 pin as output */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&audio_ext_refclk1_pins_default>;
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c3_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp3: gpio@20 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pcm3168a_1: audio-codec@44 {
|
||||
compatible = "ti,pcm3168a";
|
||||
reg = <0x44>;
|
||||
#sound-dai-cells = <1>;
|
||||
reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&audio_refclk1>;
|
||||
clock-names = "scki";
|
||||
VDD1-supply = <&vsys_3v3>;
|
||||
VDD2-supply = <&vsys_3v3>;
|
||||
VCCAD1-supply = <&vsys_5v0>;
|
||||
VCCAD2-supply = <&vsys_5v0>;
|
||||
VCCDA1-supply = <&vsys_5v0>;
|
||||
VCCDA2-supply = <&vsys_5v0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcasp0 {
|
||||
status = "okay";
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcasp0_pins_default>;
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
auxclk-fs-ratio = <256>;
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
0 0 0 1
|
||||
2 0 0 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -48,6 +48,39 @@ scm_conf: bus@100000 {
|
|||
#size-cells = <1>;
|
||||
ranges = <0x00 0x00 0x00100000 0x1c000>;
|
||||
|
||||
cpsw1_phy_gmii_sel: phy@4034 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
reg = <0x4034 0x4>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
cpsw0_phy_gmii_sel: phy@4044 {
|
||||
compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
|
||||
reg = <0x4044 0x20>;
|
||||
#phy-cells = <1>;
|
||||
ti,qsgmii-main-ports = <7>, <7>;
|
||||
};
|
||||
|
||||
pcie0_ctrl: pcie0-ctrl@4070 {
|
||||
compatible = "ti,j784s4-pcie-ctrl", "syscon";
|
||||
reg = <0x4070 0x4>;
|
||||
};
|
||||
|
||||
pcie1_ctrl: pcie1-ctrl@4074 {
|
||||
compatible = "ti,j784s4-pcie-ctrl", "syscon";
|
||||
reg = <0x4074 0x4>;
|
||||
};
|
||||
|
||||
pcie2_ctrl: pcie2-ctrl@4078 {
|
||||
compatible = "ti,j784s4-pcie-ctrl", "syscon";
|
||||
reg = <0x4078 0x4>;
|
||||
};
|
||||
|
||||
pcie3_ctrl: pcie3-ctrl@407c {
|
||||
compatible = "ti,j784s4-pcie-ctrl", "syscon";
|
||||
reg = <0x407c 0x4>;
|
||||
};
|
||||
|
||||
serdes_ln_ctrl: mux-controller@4080 {
|
||||
compatible = "reg-mux";
|
||||
reg = <0x00004080 0x30>;
|
||||
|
|
@ -75,6 +108,88 @@ serdes_ln_ctrl: mux-controller@4080 {
|
|||
<J784S4_SERDES4_LANE2_EDP_LANE2>,
|
||||
<J784S4_SERDES4_LANE3_EDP_LANE3>;
|
||||
};
|
||||
|
||||
usb_serdes_mux: mux-controller@4000 {
|
||||
compatible = "reg-mux";
|
||||
reg = <0x4000 0x4>;
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */
|
||||
};
|
||||
|
||||
ehrpwm_tbclk: clock-controller@4140 {
|
||||
compatible = "ti,am654-ehrpwm-tbclk";
|
||||
reg = <0x4140 0x18>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
audio_refclk1: clock@82e4 {
|
||||
compatible = "ti,am62-audio-refclk";
|
||||
reg = <0x82e4 0x4>;
|
||||
clocks = <&k3_clks 157 34>;
|
||||
assigned-clocks = <&k3_clks 157 34>;
|
||||
assigned-clock-parents = <&k3_clks 157 63>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
main_ehrpwm0: pwm@3000000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
reg = <0x00 0x3000000 0x00 0x100>;
|
||||
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_ehrpwm1: pwm@3010000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
reg = <0x00 0x3010000 0x00 0x100>;
|
||||
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_ehrpwm2: pwm@3020000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
reg = <0x00 0x3020000 0x00 0x100>;
|
||||
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_ehrpwm3: pwm@3030000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
reg = <0x00 0x3030000 0x00 0x100>;
|
||||
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_ehrpwm4: pwm@3040000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
reg = <0x00 0x3040000 0x00 0x100>;
|
||||
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_ehrpwm5: pwm@3050000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
reg = <0x00 0x3050000 0x00 0x100>;
|
||||
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic500: interrupt-controller@1800000 {
|
||||
|
|
@ -568,6 +683,38 @@ main_gpio6: gpio@630000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usbss0: usb@4104000 {
|
||||
bootph-all;
|
||||
compatible = "ti,j721e-usb";
|
||||
reg = <0x00 0x4104000 0x00 0x100>;
|
||||
dma-coherent;
|
||||
power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 398 21>, <&k3_clks 398 2>;
|
||||
clock-names = "ref", "lpm";
|
||||
assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */
|
||||
assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
status = "disabled"; /* Needs lane config */
|
||||
|
||||
usb0: usb@6000000 {
|
||||
bootph-all;
|
||||
compatible = "cdns,usb3";
|
||||
reg = <0x00 0x6000000 0x00 0x10000>,
|
||||
<0x00 0x6010000 0x00 0x10000>,
|
||||
<0x00 0x6020000 0x00 0x10000>;
|
||||
reg-names = "otg", "xhci", "dev";
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
|
||||
interrupt-names = "host",
|
||||
"peripheral",
|
||||
"otg";
|
||||
};
|
||||
};
|
||||
|
||||
main_i2c0: i2c@2000000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x02000000 0x00 0x100>;
|
||||
|
|
@ -907,6 +1054,122 @@ main_sdhci1: mmc@4fb0000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0_rc: pcie@2900000 {
|
||||
compatible = "ti,j784s4-pcie-host";
|
||||
reg = <0x00 0x02900000 0x00 0x1000>,
|
||||
<0x00 0x02907000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x10000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <4>;
|
||||
power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 332 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb012>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1_rc: pcie@2910000 {
|
||||
compatible = "ti,j784s4-pcie-host";
|
||||
reg = <0x00 0x02910000 0x00 0x1000>,
|
||||
<0x00 0x02917000 0x00 0x400>,
|
||||
<0x00 0x0d800000 0x00 0x00800000>,
|
||||
<0x00 0x18000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <4>;
|
||||
power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 333 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb012>;
|
||||
msi-map = <0x0 &gic_its 0x10000 0x10000>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie2_rc: pcie@2920000 {
|
||||
compatible = "ti,j784s4-pcie-host";
|
||||
reg = <0x00 0x02920000 0x00 0x1000>,
|
||||
<0x00 0x02927000 0x00 0x400>,
|
||||
<0x00 0x0e000000 0x00 0x00800000>,
|
||||
<0x44 0x00000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 334 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb012>;
|
||||
msi-map = <0x0 &gic_its 0x20000 0x10000>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie3_rc: pcie@2930000 {
|
||||
compatible = "ti,j784s4-pcie-host";
|
||||
reg = <0x00 0x02930000 0x00 0x1000>,
|
||||
<0x00 0x02937000 0x00 0x400>,
|
||||
<0x00 0x0e800000 0x00 0x00800000>,
|
||||
<0x44 0x10000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 335 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb012>;
|
||||
msi-map = <0x0 &gic_its 0x30000 0x10000>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serdes_wiz0: wiz@5060000 {
|
||||
compatible = "ti,j784s4-wiz-10g";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1427,6 +1690,180 @@ cpts@310d0000 {
|
|||
};
|
||||
};
|
||||
|
||||
main_cpsw0: ethernet@c000000 {
|
||||
compatible = "ti,j784s4-cpswxg-nuss";
|
||||
reg = <0x00 0xc000000 0x00 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-coherent;
|
||||
clocks = <&k3_clks 64 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dmas = <&main_udmap 0xca00>,
|
||||
<&main_udmap 0xca01>,
|
||||
<&main_udmap 0xca02>,
|
||||
<&main_udmap 0xca03>,
|
||||
<&main_udmap 0xca04>,
|
||||
<&main_udmap 0xca05>,
|
||||
<&main_udmap 0xca06>,
|
||||
<&main_udmap 0xca07>,
|
||||
<&main_udmap 0x4a00>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3",
|
||||
"tx4", "tx5", "tx6", "tx7",
|
||||
"rx";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
main_cpsw0_port1: port@1 {
|
||||
reg = <1>;
|
||||
label = "port1";
|
||||
ti,mac-only;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_cpsw0_port2: port@2 {
|
||||
reg = <2>;
|
||||
label = "port2";
|
||||
ti,mac-only;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_cpsw0_port3: port@3 {
|
||||
reg = <3>;
|
||||
label = "port3";
|
||||
ti,mac-only;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_cpsw0_port4: port@4 {
|
||||
reg = <4>;
|
||||
label = "port4";
|
||||
ti,mac-only;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_cpsw0_port5: port@5 {
|
||||
reg = <5>;
|
||||
label = "port5";
|
||||
ti,mac-only;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_cpsw0_port6: port@6 {
|
||||
reg = <6>;
|
||||
label = "port6";
|
||||
ti,mac-only;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_cpsw0_port7: port@7 {
|
||||
reg = <7>;
|
||||
label = "port7";
|
||||
ti,mac-only;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_cpsw0_port8: port@8 {
|
||||
reg = <8>;
|
||||
label = "port8";
|
||||
ti,mac-only;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
main_cpsw0_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x00 0xf00 0x00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 64 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,am65-cpts";
|
||||
reg = <0x00 0x3d000 0x00 0x400>;
|
||||
clocks = <&k3_clks 64 3>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
main_cpsw1: ethernet@c200000 {
|
||||
compatible = "ti,j721e-cpsw-nuss";
|
||||
reg = <0x00 0xc200000 0x00 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-coherent;
|
||||
clocks = <&k3_clks 62 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dmas = <&main_udmap 0xc640>,
|
||||
<&main_udmap 0xc641>,
|
||||
<&main_udmap 0xc642>,
|
||||
<&main_udmap 0xc643>,
|
||||
<&main_udmap 0xc644>,
|
||||
<&main_udmap 0xc645>,
|
||||
<&main_udmap 0xc646>,
|
||||
<&main_udmap 0xc647>,
|
||||
<&main_udmap 0x4640>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3",
|
||||
"tx4", "tx5", "tx6", "tx7",
|
||||
"rx";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
main_cpsw1_port1: port@1 {
|
||||
reg = <1>;
|
||||
label = "port1";
|
||||
phys = <&cpsw1_phy_gmii_sel 1>;
|
||||
ti,mac-only;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
main_cpsw1_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
|
||||
reg = <0x00 0xf00 0x00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 62 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,am65-cpts";
|
||||
reg = <0x00 0x3d000 0x00 0x400>;
|
||||
clocks = <&k3_clks 62 3>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
main_mcan0: can@2701000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x02701000 0x00 0x200>,
|
||||
|
|
@ -2255,4 +2692,94 @@ dss_ports: ports {
|
|||
*/
|
||||
};
|
||||
};
|
||||
|
||||
mcasp0: mcasp@2b00000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x00 0x02b00000 0x00 0x2000>,
|
||||
<0x00 0x02b08000 0x00 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&k3_clks 265 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 265 0>;
|
||||
assigned-clock-parents = <&k3_clks 265 1>;
|
||||
power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp1: mcasp@2b10000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x00 0x02b10000 0x00 0x2000>,
|
||||
<0x00 0x02b18000 0x00 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&k3_clks 266 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 266 0>;
|
||||
assigned-clock-parents = <&k3_clks 266 1>;
|
||||
power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp2: mcasp@2b20000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x00 0x02b20000 0x00 0x2000>,
|
||||
<0x00 0x02b28000 0x00 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&k3_clks 267 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 267 0>;
|
||||
assigned-clock-parents = <&k3_clks 267 1>;
|
||||
power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp3: mcasp@2b30000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x00 0x02b30000 0x00 0x2000>,
|
||||
<0x00 0x02b38000 0x00 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&k3_clks 268 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 268 0>;
|
||||
assigned-clock-parents = <&k3_clks 268 1>;
|
||||
power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp4: mcasp@2b40000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x00 0x02b40000 0x00 0x2000>,
|
||||
<0x00 0x02b48000 0x00 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&k3_clks 269 0>;
|
||||
clock-names = "fck";
|
||||
assigned-clocks = <&k3_clks 269 0>;
|
||||
assigned-clock-parents = <&k3_clks 269 1>;
|
||||
power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -145,12 +145,16 @@ mcu_timerio_output: pinctrl@40f04280 {
|
|||
status = "reserved";
|
||||
};
|
||||
|
||||
mcu_conf: syscon@40f00000 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00 0x40f00000 0x00 0x20000>;
|
||||
mcu_conf: bus@40f00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00 0x00 0x40f00000 0x20000>;
|
||||
ranges = <0x0 0x0 0x40f00000 0x20000>;
|
||||
|
||||
cpsw_mac_syscon: ethernet-mac-syscon@200 {
|
||||
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
|
||||
reg = <0x200 0x8>;
|
||||
};
|
||||
|
||||
phy_gmii_sel: phy@4040 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
|
|
@ -553,7 +557,7 @@ mcu_cpsw_port1: port@1 {
|
|||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||
ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -238,7 +238,10 @@ cbass_main: bus@100000 {
|
|||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||
<0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
|
||||
<0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
|
||||
<0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
|
||||
<0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
|
||||
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
|
||||
|
|
@ -248,7 +251,12 @@ cbass_main: bus@100000 {
|
|||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
|
||||
<0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
|
||||
<0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
|
||||
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
|
||||
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
|
||||
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
|
||||
|
||||
/* MCUSS_WKUP Range */
|
||||
|
|
|
|||
|
|
@ -38,6 +38,9 @@
|
|||
#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT)
|
||||
#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT)
|
||||
|
||||
/* Default mux configuration for gpio-ranges to use with pinctrl */
|
||||
#define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7)
|
||||
|
||||
#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
|
|
|
|||
|
|
@ -201,4 +201,12 @@
|
|||
#define J784S4_SERDES4_LANE3_USB 0x2
|
||||
#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
|
||||
|
||||
/* J722S */
|
||||
|
||||
#define J722S_SERDES0_LANE0_USB 0x0
|
||||
#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
|
||||
|
||||
#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0
|
||||
#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1
|
||||
|
||||
#endif /* DTS_ARM64_TI_K3_SERDES_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user