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drm/amd/pm: Use gpu metrics 1.9 for SMUv13.0.6
Fill and publish GPU metrics in v1.9 format for SMUv13.0.6 SOCs Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar
Alex Deucher
parent
c3cd00fea6
commit
b4f748f22d
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@ -550,6 +550,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)
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struct smu_table_context *smu_table = &smu->smu_table;
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struct smu_table *tables = smu_table->tables;
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void *gpu_metrics_table __free(kfree) = NULL;
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struct smu_v13_0_6_gpu_metrics *gpu_metrics;
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void *driver_pptable __free(kfree) = NULL;
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void *metrics_table __free(kfree) = NULL;
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struct amdgpu_device *adev = smu->adev;
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@ -589,11 +590,22 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)
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if (!driver_pptable)
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return -ENOMEM;
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ret = smu_table_cache_init(smu, SMU_TABLE_SMU_METRICS,
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sizeof(struct smu_v13_0_6_gpu_metrics), 1);
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if (ret)
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return ret;
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gpu_metrics = (struct smu_v13_0_6_gpu_metrics
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*)(tables[SMU_TABLE_SMU_METRICS].cache.buffer);
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smu_v13_0_6_gpu_metrics_init(gpu_metrics, 1, 9);
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if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
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IP_VERSION(13, 0, 12)) {
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ret = smu_v13_0_12_tables_init(smu);
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if (ret)
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if (ret) {
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smu_table_cache_fini(smu, SMU_TABLE_SMU_METRICS);
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return ret;
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}
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}
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smu_table->gpu_metrics_table = no_free_ptr(gpu_metrics_table);
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@ -732,6 +744,7 @@ static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu)
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{
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if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
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smu_v13_0_12_tables_fini(smu);
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smu_table_cache_fini(smu, SMU_TABLE_SMU_METRICS);
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return smu_v13_0_fini_smc_tables(smu);
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}
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@ -2762,18 +2775,16 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id,
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static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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struct gpu_metrics_v1_8 *gpu_metrics =
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(struct gpu_metrics_v1_8 *)smu_table->gpu_metrics_table;
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struct smu_table *tables = smu_table->tables;
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struct smu_v13_0_6_gpu_metrics *gpu_metrics;
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int version = smu_v13_0_6_get_metrics_version(smu);
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MetricsTableV0_t *metrics_v0 __free(kfree) = NULL;
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int ret = 0, xcc_id, inst, i, j, k, idx;
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struct amdgpu_device *adev = smu->adev;
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int ret = 0, xcc_id, inst, i, j;
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MetricsTableV1_t *metrics_v1;
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MetricsTableV2_t *metrics_v2;
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struct amdgpu_xcp *xcp;
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u16 link_width_level;
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u8 num_jpeg_rings;
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u32 inst_mask;
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bool per_inst;
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metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
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@ -2788,8 +2799,8 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
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metrics_v1 = (MetricsTableV1_t *)metrics_v0;
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metrics_v2 = (MetricsTableV2_t *)metrics_v0;
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smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 8);
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gpu_metrics = (struct smu_v13_0_6_gpu_metrics
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*)(tables[SMU_TABLE_SMU_METRICS].cache.buffer);
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gpu_metrics->temperature_hotspot =
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SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version));
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@ -2911,55 +2922,49 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
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gpu_metrics->xgmi_link_status[j] = ret;
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}
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gpu_metrics->num_partition = adev->xcp_mgr->num_xcps;
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per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
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num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
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for_each_xcp(adev->xcp_mgr, xcp, i) {
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amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
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idx = 0;
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for_each_inst(k, inst_mask) {
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/* Both JPEG and VCN has same instances */
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inst = GET_INST(VCN, k);
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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inst = GET_INST(JPEG, i);
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for (j = 0; j < num_jpeg_rings; ++j)
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gpu_metrics->jpeg_busy[(i * num_jpeg_rings) + j] =
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SMUQ10_ROUND(GET_METRIC_FIELD(
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JpegBusy,
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version)[(inst * num_jpeg_rings) + j]);
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}
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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inst = GET_INST(VCN, i);
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gpu_metrics->vcn_busy[i] =
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SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
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}
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for (j = 0; j < num_jpeg_rings; ++j) {
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gpu_metrics->xcp_stats[i].jpeg_busy
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[(idx * num_jpeg_rings) + j] =
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SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version)
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[(inst * num_jpeg_rings) + j]);
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}
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gpu_metrics->xcp_stats[i].vcn_busy[idx] =
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SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
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idx++;
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}
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if (per_inst) {
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amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
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idx = 0;
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for_each_inst(k, inst_mask) {
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inst = GET_INST(GC, k);
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gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
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SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
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gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
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SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,
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version)[inst]);
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if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) {
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gpu_metrics->xcp_stats[i].gfx_below_host_limit_ppt_acc[idx] =
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SMUQ10_ROUND
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(metrics_v0->GfxclkBelowHostLimitPptAcc[inst]);
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gpu_metrics->xcp_stats[i].gfx_below_host_limit_thm_acc[idx] =
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SMUQ10_ROUND
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(metrics_v0->GfxclkBelowHostLimitThmAcc[inst]);
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gpu_metrics->xcp_stats[i].gfx_low_utilization_acc[idx] =
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SMUQ10_ROUND
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(metrics_v0->GfxclkLowUtilizationAcc[inst]);
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gpu_metrics->xcp_stats[i].gfx_below_host_limit_total_acc[idx] =
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SMUQ10_ROUND
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(metrics_v0->GfxclkBelowHostLimitTotalAcc[inst]);
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}
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idx++;
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if (per_inst) {
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for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) {
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inst = GET_INST(GC, i);
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gpu_metrics->gfx_busy_inst[i] = SMUQ10_ROUND(
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GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
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gpu_metrics->gfx_busy_acc[i] = SMUQ10_ROUND(
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GET_GPU_METRIC_FIELD(GfxBusyAcc,
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version)[inst]);
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if (smu_v13_0_6_cap_supported(
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smu, SMU_CAP(HST_LIMIT_METRICS))) {
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gpu_metrics->gfx_below_host_limit_ppt_acc
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[i] = SMUQ10_ROUND(
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metrics_v0->GfxclkBelowHostLimitPptAcc
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[inst]);
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gpu_metrics->gfx_below_host_limit_thm_acc
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[i] = SMUQ10_ROUND(
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metrics_v0->GfxclkBelowHostLimitThmAcc
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[inst]);
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gpu_metrics->gfx_low_utilization_acc
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[i] = SMUQ10_ROUND(
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metrics_v0
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->GfxclkLowUtilizationAcc[inst]);
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gpu_metrics->gfx_below_host_limit_total_acc
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[i] = SMUQ10_ROUND(
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metrics_v0->GfxclkBelowHostLimitTotalAcc
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[inst]);
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}
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}
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}
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@ -2969,7 +2974,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
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gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
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*table = (void *)gpu_metrics;
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*table = tables[SMU_TABLE_SMU_METRICS].cache.buffer;
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return sizeof(*gpu_metrics);
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}
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@ -75,6 +75,13 @@ enum smu_v13_0_6_caps {
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SMU_CAP(ALL),
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};
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#define SMU_13_0_6_NUM_XGMI_LINKS 8
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#define SMU_13_0_6_MAX_GFX_CLKS 8
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#define SMU_13_0_6_MAX_CLKS 4
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#define SMU_13_0_6_MAX_XCC 8
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#define SMU_13_0_6_MAX_VCN 4
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#define SMU_13_0_6_MAX_JPEG 40
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extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu);
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bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap);
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int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu);
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@ -99,4 +106,117 @@ int smu_v13_0_12_get_npm_data(struct smu_context *smu,
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extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[];
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extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[];
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extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs;
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#if defined(SWSMU_CODE_LAYER_L2)
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#include "smu_cmn.h"
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/* SMUv 13.0.6 GPU metrics*/
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#define SMU_13_0_6_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \
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SMU_SCALAR(SMU_MATTR(TEMPERATURE_HOTSPOT), SMU_MUNIT(TEMP_1), \
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SMU_MTYPE(U16), temperature_hotspot); \
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SMU_SCALAR(SMU_MATTR(TEMPERATURE_MEM), SMU_MUNIT(TEMP_1), \
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SMU_MTYPE(U16), temperature_mem); \
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SMU_SCALAR(SMU_MATTR(TEMPERATURE_VRSOC), SMU_MUNIT(TEMP_1), \
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SMU_MTYPE(U16), temperature_vrsoc); \
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SMU_SCALAR(SMU_MATTR(CURR_SOCKET_POWER), SMU_MUNIT(POWER_1), \
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SMU_MTYPE(U16), curr_socket_power); \
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SMU_SCALAR(SMU_MATTR(AVERAGE_GFX_ACTIVITY), SMU_MUNIT(PERCENT), \
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SMU_MTYPE(U16), average_gfx_activity); \
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SMU_SCALAR(SMU_MATTR(AVERAGE_UMC_ACTIVITY), SMU_MUNIT(PERCENT), \
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SMU_MTYPE(U16), average_umc_activity); \
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SMU_SCALAR(SMU_MATTR(MEM_MAX_BANDWIDTH), SMU_MUNIT(BW_1), \
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SMU_MTYPE(U64), mem_max_bandwidth); \
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SMU_SCALAR(SMU_MATTR(ENERGY_ACCUMULATOR), SMU_MUNIT(NONE), \
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SMU_MTYPE(U64), energy_accumulator); \
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SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1), \
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SMU_MTYPE(U64), system_clock_counter); \
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SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \
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SMU_MTYPE(U32), accumulation_counter); \
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SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U32), prochot_residency_acc); \
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SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U32), ppt_residency_acc); \
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SMU_SCALAR(SMU_MATTR(SOCKET_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U32), socket_thm_residency_acc); \
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SMU_SCALAR(SMU_MATTR(VR_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U32), vr_thm_residency_acc); \
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SMU_SCALAR(SMU_MATTR(HBM_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U32), hbm_thm_residency_acc); \
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SMU_SCALAR(SMU_MATTR(GFXCLK_LOCK_STATUS), SMU_MUNIT(NONE), \
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SMU_MTYPE(U32), gfxclk_lock_status); \
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SMU_SCALAR(SMU_MATTR(PCIE_LINK_WIDTH), SMU_MUNIT(NONE), \
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SMU_MTYPE(U16), pcie_link_width); \
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SMU_SCALAR(SMU_MATTR(PCIE_LINK_SPEED), SMU_MUNIT(SPEED_2), \
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SMU_MTYPE(U16), pcie_link_speed); \
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SMU_SCALAR(SMU_MATTR(XGMI_LINK_WIDTH), SMU_MUNIT(NONE), \
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SMU_MTYPE(U16), xgmi_link_width); \
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SMU_SCALAR(SMU_MATTR(XGMI_LINK_SPEED), SMU_MUNIT(SPEED_1), \
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SMU_MTYPE(U16), xgmi_link_speed); \
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SMU_SCALAR(SMU_MATTR(GFX_ACTIVITY_ACC), SMU_MUNIT(PERCENT), \
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SMU_MTYPE(U32), gfx_activity_acc); \
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SMU_SCALAR(SMU_MATTR(MEM_ACTIVITY_ACC), SMU_MUNIT(PERCENT), \
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SMU_MTYPE(U32), mem_activity_acc); \
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SMU_SCALAR(SMU_MATTR(PCIE_BANDWIDTH_ACC), SMU_MUNIT(PERCENT), \
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SMU_MTYPE(U64), pcie_bandwidth_acc); \
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SMU_SCALAR(SMU_MATTR(PCIE_BANDWIDTH_INST), SMU_MUNIT(BW_1), \
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SMU_MTYPE(U64), pcie_bandwidth_inst); \
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SMU_SCALAR(SMU_MATTR(PCIE_L0_TO_RECOV_COUNT_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U64), pcie_l0_to_recov_count_acc); \
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SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_COUNT_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U64), pcie_replay_count_acc); \
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SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_ROVER_COUNT_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U64), pcie_replay_rover_count_acc); \
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SMU_SCALAR(SMU_MATTR(PCIE_NAK_SENT_COUNT_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U32), pcie_nak_sent_count_acc); \
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SMU_SCALAR(SMU_MATTR(PCIE_NAK_RCVD_COUNT_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U32), pcie_nak_rcvd_count_acc); \
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SMU_ARRAY(SMU_MATTR(XGMI_READ_DATA_ACC), SMU_MUNIT(DATA_1), \
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SMU_MTYPE(U64), xgmi_read_data_acc, \
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SMU_13_0_6_NUM_XGMI_LINKS); \
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SMU_ARRAY(SMU_MATTR(XGMI_WRITE_DATA_ACC), SMU_MUNIT(DATA_1), \
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SMU_MTYPE(U64), xgmi_write_data_acc, \
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SMU_13_0_6_NUM_XGMI_LINKS); \
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SMU_ARRAY(SMU_MATTR(XGMI_LINK_STATUS), SMU_MUNIT(NONE), \
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SMU_MTYPE(U16), xgmi_link_status, \
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SMU_13_0_6_NUM_XGMI_LINKS); \
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SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \
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SMU_MTYPE(U64), firmware_timestamp); \
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SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \
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SMU_MTYPE(U16), current_gfxclk, SMU_13_0_6_MAX_GFX_CLKS); \
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SMU_ARRAY(SMU_MATTR(CURRENT_SOCCLK), SMU_MUNIT(CLOCK_1), \
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SMU_MTYPE(U16), current_socclk, SMU_13_0_6_MAX_CLKS); \
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SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \
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SMU_MTYPE(U16), current_vclk0, SMU_13_0_6_MAX_CLKS); \
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SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \
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SMU_MTYPE(U16), current_dclk0, SMU_13_0_6_MAX_CLKS); \
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SMU_SCALAR(SMU_MATTR(CURRENT_UCLK), SMU_MUNIT(CLOCK_1), \
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SMU_MTYPE(U16), current_uclk); \
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SMU_SCALAR(SMU_MATTR(PCIE_LC_PERF_OTHER_END_RECOVERY), \
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SMU_MUNIT(NONE), SMU_MTYPE(U32), \
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pcie_lc_perf_other_end_recovery); \
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SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \
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SMU_MTYPE(U32), gfx_busy_inst, SMU_13_0_6_MAX_XCC); \
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SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \
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jpeg_busy, SMU_13_0_6_MAX_JPEG); \
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SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \
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vcn_busy, SMU_13_0_6_MAX_VCN); \
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SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(PERCENT), SMU_MTYPE(U64), \
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gfx_busy_acc, SMU_13_0_6_MAX_XCC); \
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SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \
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SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \
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SMU_13_0_6_MAX_XCC); \
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SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \
|
||||
SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \
|
||||
SMU_13_0_6_MAX_XCC); \
|
||||
SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \
|
||||
SMU_MTYPE(U64), gfx_low_utilization_acc, \
|
||||
SMU_13_0_6_MAX_XCC); \
|
||||
SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \
|
||||
SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \
|
||||
SMU_13_0_6_MAX_XCC);
|
||||
|
||||
DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_gpu_metrics, SMU_13_0_6_METRICS_FIELDS);
|
||||
|
||||
#endif /* SWSMU_CODE_LAYER_L2 */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user