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drm/amd/display: Update IPS sequential_ono requirement checks

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[why & how]
ASICs that require special RCG/PG programming are determined based
on hw_internal_rev. Update these checks to properly include all such
ASICs.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ovidiu Bunea <Ovidiu.Bunea@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ovidiu Bunea 2025-04-10 11:00:08 -04:00 committed by Alex Deucher
parent da072da2c8
commit b4db797117
3 changed files with 3 additions and 3 deletions
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2
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
View File

@ -138,7 +138,7 @@ bool dpp35_construct(
dpp->base.funcs = &dcn35_dpp_funcs;
// w/a for cursor memory stuck in LS by programming DISPCLK_R_GATE_DISABLE, limit w/a to some ASIC revs
if (dpp->base.ctx->asic_id.hw_internal_rev <= 0x10)
if (dpp->base.ctx->asic_id.hw_internal_rev < 0x40)
dpp->dispclk_r_gate_disable = true;
return ret;
}

2
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
View File

@ -1903,7 +1903,7 @@ static bool dcn35_resource_construct(
dc->caps.max_disp_clock_khz_at_vmin = 650000;
/* Sequential ONO is based on ASIC. */
if (dc->ctx->asic_id.hw_internal_rev > 0x10)
if (dc->ctx->asic_id.hw_internal_rev >= 0x40)
dc->caps.sequential_ono = true;
/* Use pipe context based otg sync logic */

2
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
View File

@ -1876,7 +1876,7 @@ static bool dcn36_resource_construct(
dc->caps.max_disp_clock_khz_at_vmin = 650000;
/* Sequential ONO is based on ASIC. */
if (dc->ctx->asic_id.hw_internal_rev > 0x10)
if (dc->ctx->asic_id.hw_internal_rev >= 0x40)
dc->caps.sequential_ono = true;
/* Use pipe context based otg sync logic */