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Merge branch '20240611133752.2192401-1-quic_ajipan@quicinc.com' into clk-for-6.12

Browse Source 
Merge the SM4450 display, camera and GPU bindings through a topic
branch, to make it possible to merge them into the DeviceTree source
branch as well.
This commit is contained in:
Bjorn Andersson 2024-08-14 21:05:26 -05:00
commit b4c71885e5
6 changed files with 355 additions and 0 deletions
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63
Documentation/devicetree/bindings/clock/qcom,sm4450-camcc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
properties:
compatible:
const: qcom,sm4450-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock source from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@ade0000 {
compatible = "qcom,sm4450-camcc";
reg = <0x0ade0000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

71
Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
properties:
compatible:
const: qcom,sm4450-dispcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Display AHB clock source from GCC
- description: sleep clock source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@af00000 {
compatible = "qcom,sm4450-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy_pll_out_byteclk>,
<&dsi0_phy_pll_out_dsiclk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
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@ -14,6 +14,7 @@ description: |
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,sm4450-gpucc.h
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
@ -23,6 +24,7 @@ description: |
properties:
compatible:
enum:
- qcom,sm4450-gpucc
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc

106
include/dt-bindings/clock/qcom,sm4450-camcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_AREG_CLK 1
#define CAM_CC_BPS_CLK 2
#define CAM_CC_BPS_CLK_SRC 3
#define CAM_CC_CAMNOC_ATB_CLK 4
#define CAM_CC_CAMNOC_AXI_CLK 5
#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
#define CAM_CC_CAMNOC_AXI_HF_CLK 7
#define CAM_CC_CAMNOC_AXI_SF_CLK 8
#define CAM_CC_CCI_0_CLK 9
#define CAM_CC_CCI_0_CLK_SRC 10
#define CAM_CC_CCI_1_CLK 11
#define CAM_CC_CCI_1_CLK_SRC 12
#define CAM_CC_CORE_AHB_CLK 13
#define CAM_CC_CPAS_AHB_CLK 14
#define CAM_CC_CPHY_RX_CLK_SRC 15
#define CAM_CC_CRE_AHB_CLK 16
#define CAM_CC_CRE_CLK 17
#define CAM_CC_CRE_CLK_SRC 18
#define CAM_CC_CSI0PHYTIMER_CLK 19
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20
#define CAM_CC_CSI1PHYTIMER_CLK 21
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22
#define CAM_CC_CSI2PHYTIMER_CLK 23
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24
#define CAM_CC_CSIPHY0_CLK 25
#define CAM_CC_CSIPHY1_CLK 26
#define CAM_CC_CSIPHY2_CLK 27
#define CAM_CC_FAST_AHB_CLK_SRC 28
#define CAM_CC_ICP_ATB_CLK 29
#define CAM_CC_ICP_CLK 30
#define CAM_CC_ICP_CLK_SRC 31
#define CAM_CC_ICP_CTI_CLK 32
#define CAM_CC_ICP_TS_CLK 33
#define CAM_CC_MCLK0_CLK 34
#define CAM_CC_MCLK0_CLK_SRC 35
#define CAM_CC_MCLK1_CLK 36
#define CAM_CC_MCLK1_CLK_SRC 37
#define CAM_CC_MCLK2_CLK 38
#define CAM_CC_MCLK2_CLK_SRC 39
#define CAM_CC_MCLK3_CLK 40
#define CAM_CC_MCLK3_CLK_SRC 41
#define CAM_CC_OPE_0_AHB_CLK 42
#define CAM_CC_OPE_0_AREG_CLK 43
#define CAM_CC_OPE_0_CLK 44
#define CAM_CC_OPE_0_CLK_SRC 45
#define CAM_CC_PLL0 46
#define CAM_CC_PLL0_OUT_EVEN 47
#define CAM_CC_PLL0_OUT_ODD 48
#define CAM_CC_PLL1 49
#define CAM_CC_PLL1_OUT_EVEN 50
#define CAM_CC_PLL2 51
#define CAM_CC_PLL2_OUT_EVEN 52
#define CAM_CC_PLL3 53
#define CAM_CC_PLL3_OUT_EVEN 54
#define CAM_CC_PLL4 55
#define CAM_CC_PLL4_OUT_EVEN 56
#define CAM_CC_SLOW_AHB_CLK_SRC 57
#define CAM_CC_SOC_AHB_CLK 58
#define CAM_CC_SYS_TMR_CLK 59
#define CAM_CC_TFE_0_AHB_CLK 60
#define CAM_CC_TFE_0_CLK 61
#define CAM_CC_TFE_0_CLK_SRC 62
#define CAM_CC_TFE_0_CPHY_RX_CLK 63
#define CAM_CC_TFE_0_CSID_CLK 64
#define CAM_CC_TFE_0_CSID_CLK_SRC 65
#define CAM_CC_TFE_1_AHB_CLK 66
#define CAM_CC_TFE_1_CLK 67
#define CAM_CC_TFE_1_CLK_SRC 68
#define CAM_CC_TFE_1_CPHY_RX_CLK 69
#define CAM_CC_TFE_1_CSID_CLK 70
#define CAM_CC_TFE_1_CSID_CLK_SRC 71
/* CAM_CC power domains */
#define CAM_CC_CAMSS_TOP_GDSC 0
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_CAMNOC_BCR 1
#define CAM_CC_CAMSS_TOP_BCR 2
#define CAM_CC_CCI_0_BCR 3
#define CAM_CC_CCI_1_BCR 4
#define CAM_CC_CPAS_BCR 5
#define CAM_CC_CRE_BCR 6
#define CAM_CC_CSI0PHY_BCR 7
#define CAM_CC_CSI1PHY_BCR 8
#define CAM_CC_CSI2PHY_BCR 9
#define CAM_CC_ICP_BCR 10
#define CAM_CC_MCLK0_BCR 11
#define CAM_CC_MCLK1_BCR 12
#define CAM_CC_MCLK2_BCR 13
#define CAM_CC_MCLK3_BCR 14
#define CAM_CC_OPE_0_BCR 15
#define CAM_CC_TFE_0_BCR 16
#define CAM_CC_TFE_1_BCR 17
#endif

51
include/dt-bindings/clock/qcom,sm4450-dispcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_AHB1_CLK 0
#define DISP_CC_MDSS_AHB_CLK 1
#define DISP_CC_MDSS_AHB_CLK_SRC 2
#define DISP_CC_MDSS_BYTE0_CLK 3
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
#define DISP_CC_MDSS_ESC0_CLK 7
#define DISP_CC_MDSS_ESC0_CLK_SRC 8
#define DISP_CC_MDSS_MDP1_CLK 9
#define DISP_CC_MDSS_MDP_CLK 10
#define DISP_CC_MDSS_MDP_CLK_SRC 11
#define DISP_CC_MDSS_MDP_LUT1_CLK 12
#define DISP_CC_MDSS_MDP_LUT_CLK 13
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 14
#define DISP_CC_MDSS_PCLK0_CLK 15
#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
#define DISP_CC_MDSS_ROT1_CLK 17
#define DISP_CC_MDSS_ROT_CLK 18
#define DISP_CC_MDSS_ROT_CLK_SRC 19
#define DISP_CC_MDSS_RSCC_AHB_CLK 20
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 21
#define DISP_CC_MDSS_VSYNC1_CLK 22
#define DISP_CC_MDSS_VSYNC_CLK 23
#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
#define DISP_CC_PLL0 25
#define DISP_CC_PLL1 26
#define DISP_CC_SLEEP_CLK 27
#define DISP_CC_SLEEP_CLK_SRC 28
#define DISP_CC_XO_CLK 29
#define DISP_CC_XO_CLK_SRC 30
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
#define DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif

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include/dt-bindings/clock/qcom,sm4450-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CB_CLK 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_FF_CLK 3
#define GPU_CC_CX_GFX3D_CLK 4
#define GPU_CC_CX_GFX3D_SLV_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CX_SNOC_DVM_CLK 7
#define GPU_CC_CXO_AON_CLK 8
#define GPU_CC_CXO_CLK 9
#define GPU_CC_DEMET_CLK 10
#define GPU_CC_DEMET_DIV_CLK_SRC 11
#define GPU_CC_FF_CLK_SRC 12
#define GPU_CC_FREQ_MEASURE_CLK 13
#define GPU_CC_GMU_CLK_SRC 14
#define GPU_CC_GX_CXO_CLK 15
#define GPU_CC_GX_FF_CLK 16
#define GPU_CC_GX_GFX3D_CLK 17
#define GPU_CC_GX_GFX3D_CLK_SRC 18
#define GPU_CC_GX_GFX3D_RDVM_CLK 19
#define GPU_CC_GX_GMU_CLK 20
#define GPU_CC_GX_VSENSE_CLK 21
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 22
#define GPU_CC_HUB_AON_CLK 23
#define GPU_CC_HUB_CLK_SRC 24
#define GPU_CC_HUB_CX_INT_CLK 25
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 26
#define GPU_CC_MEMNOC_GFX_CLK 27
#define GPU_CC_MND1X_0_GFX3D_CLK 28
#define GPU_CC_PLL0 29
#define GPU_CC_PLL1 30
#define GPU_CC_SLEEP_CLK 31
#define GPU_CC_XO_CLK_SRC 32
#define GPU_CC_XO_DIV_CLK_SRC 33
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GPU_CC_GX_GDSC 1
/* GPU_CC resets */
#define GPU_CC_ACD_BCR 0
#define GPU_CC_CB_BCR 1
#define GPU_CC_CX_BCR 2
#define GPU_CC_FAST_HUB_BCR 3
#define GPU_CC_FF_BCR 4
#define GPU_CC_GFX3D_AON_BCR 5
#define GPU_CC_GMU_BCR 6
#define GPU_CC_GX_BCR 7
#define GPU_CC_XO_BCR 8
#define GPU_CC_GX_ACD_IROOT_BCR 9
#define GPU_CC_RBCPR_BCR 10
#endif