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riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores

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Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse
provides a forward progress guarantee on LR/SC sequences in main
memory regions with cacheability and coherence PMAs.

The SpacemiT X100 core supports it per the SpacemiT K3 hardware
specification.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Yixun lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
This commit is contained in:
Guodong Xu 2026-05-26 15:22:58 -04:00 committed by Yixun Lan
parent cfe5c91cb7
commit b4a789799d
1 changed files with 8 additions and 8 deletions
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16
arch/riscv/boot/dts/spacemit/k3.dtsi
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@ -36,7 +36,7 @@ cpu_0: cpu@0 {
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "zicntr",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@ -77,7 +77,7 @@ cpu_1: cpu@1 {
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "zicntr",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@ -118,7 +118,7 @@ cpu_2: cpu@2 {
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "zicntr",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@ -159,7 +159,7 @@ cpu_3: cpu@3 {
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "zicntr",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@ -200,7 +200,7 @@ cpu_4: cpu@4 {
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "zicntr",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@ -241,7 +241,7 @@ cpu_5: cpu@5 {
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "zicntr",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@ -282,7 +282,7 @@ cpu_6: cpu@6 {
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "zicntr",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@ -323,7 +323,7 @@ cpu_7: cpu@7 {
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
"ziccamoa", "ziccif", "zicclsm", "zicntr",
"ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
"zicond", "zicsr", "zifencei", "zihintntl",
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",