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x86/cpu changes for v7.0:
- amd: Correct the microcode table for Zenbleed
- amd: Use ZEN_MODEL_STEP_UCODE() for erratum_1386_microcode[]
- Drop vestigial PBE logic in AMD/Hygon/Centaur/Cyrix
(Andrew Cooper)
- tsx: Set default TSX mode to auto (Nikolay Borisov)
- Drop unused Kconfig symbol X86_P6_NOP (Randy Dunlap)
Signed-off-by: Ingo Molnar <mingo@kernel.org>
-----BEGIN PGP SIGNATURE-----
iQJFBAABCgAvFiEEBpT5eoXrXCwVQwEKEnMQ0APhK1gFAmmJlU0RHG1pbmdvQGtl
cm5lbC5vcmcACgkQEnMQ0APhK1hVaBAArtXnP3nah0R6UphYGbFew9G5cLHXwhgZ
bUs9j6NbeJhEZBiXQON0Jfy2ucwePMOB+75+UlIm6VnKMHhE+ayB6H4zihSWirgb
Q0CzjwlT+mZ9hRxnG9o3QcbwbSmnTAwyCAcQuEpTYYKW5vqiMaKoXt8iMIwbWNcT
0hX3pLzpfbOjrXgyjGzRk5nj9JZvpL3rdmOi+/7tsDoKgsfbyOKudP/PV5OuZ2mC
9CyQCW00nAUN5+Lq8zZFBkbJS71mI78wdE3uC3NgUENhOFLccQERxdPUyVdx9K38
dXyaRfc61OOxG+RDQH5etGSexKgXrbaE22hasMVCypBP0PP66GeLJZFArOS5Pa2s
39r9NaCALyZZ76gyxceSJ1B1pOsX8MPgC2+WVW2HxZBeOxcUOEcsTRdCthZkb2w9
kg+Fa9ITMzG01yqCT6WtIfADAPxa8FpVk/q4qBTCG/WkPrq9APSKLsj6NLfHM6MM
ZesXoBULiSOED3oypglGbItsIPyWHpIumpObWdTR/U3Z1K/xCRY1qAgfjMHkajrm
8brSnEDYPOdFpvDNCaJnwrnWJwu1YY3qcuVvVvJPzdWNUff0hpIXnn63S+FegVfX
J5velNq+GlHvvh2yZgV8jUVpeqqckIP4/SS3z0sH+QcXXDoJWgyQqwbhx1M7a61m
1UDI1V8K0vo=
=k5rk
-----END PGP SIGNATURE-----
Merge tag 'x86-cpu-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu updates from Ingo Molnar:
- CPU model updates (Andrew Cooper):
- amd: Correct the microcode table for Zenbleed
- amd: Use ZEN_MODEL_STEP_UCODE() for erratum_1386_microcode[]
- Drop vestigial PBE logic in AMD/Hygon/Centaur/Cyrix
- tsx: Set default TSX mode to auto (Nikolay Borisov)
- Drop unused Kconfig symbol X86_P6_NOP (Randy Dunlap)
* tag 'x86-cpu-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/tsx: Set default TSX mode to auto
x86/cpu: Drop unused Kconfig symbol X86_P6_NOP
x86/cpu: Drop vestigial PBE logic in AMD/Hygon/Centaur/Cyrix
x86/cpu/amd: Use ZEN_MODEL_STEP_UCODE() for erratum_1386_microcode[]
x86/cpu/amd: Correct the microcode table for Zenbleed
This commit is contained in:
Linus Torvalds
commit
b490d2a83f
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@ -1817,7 +1817,7 @@ config ARCH_PKEY_BITS
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choice
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prompt "TSX enable mode"
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depends on CPU_SUP_INTEL
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default X86_INTEL_TSX_MODE_OFF
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default X86_INTEL_TSX_MODE_AUTO
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help
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Intel's TSX (Transactional Synchronization Extensions) feature
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allows to optimize locking protocols through lock elision which
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@ -38,7 +38,7 @@ config X86_REQUIRED_FEATURE_ALWAYS
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config X86_REQUIRED_FEATURE_NOPL
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def_bool y
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depends on X86_64 || X86_P6_NOP
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depends on X86_64
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config X86_REQUIRED_FEATURE_CX8
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def_bool y
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@ -42,9 +42,3 @@ cflags-$(CONFIG_MGEODE_LX) += $(call cc-option,-march=geode,-march=pentium-mmx)
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# add at the end to overwrite eventual tuning options from earlier
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# cpu entries
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cflags-$(CONFIG_X86_GENERIC) += $(call tune,generic,$(call tune,i686))
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# Bug fix for binutils: this option is required in order to keep
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# binutils from generating NOPL instructions against our will.
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ifneq ($(CONFIG_X86_P6_NOP),y)
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cflags-y += $(call cc-option,-Wa$(comma)-mtune=generic32,)
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endif
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@ -873,8 +873,8 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
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}
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static const struct x86_cpu_id erratum_1386_microcode[] = {
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X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x01), 0x2, 0x2, 0x0800126e),
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X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x31), 0x0, 0x0, 0x08301052),
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ZEN_MODEL_STEP_UCODE(0x17, 0x01, 0x2, 0x0800126e),
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ZEN_MODEL_STEP_UCODE(0x17, 0x31, 0x0, 0x08301052),
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{}
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};
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@ -951,26 +951,14 @@ static void init_amd_zen1(struct cpuinfo_x86 *c)
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}
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}
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static bool cpu_has_zenbleed_microcode(void)
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{
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u32 good_rev = 0;
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switch (boot_cpu_data.x86_model) {
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case 0x30 ... 0x3f: good_rev = 0x0830107b; break;
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case 0x60 ... 0x67: good_rev = 0x0860010c; break;
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case 0x68 ... 0x6f: good_rev = 0x08608107; break;
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case 0x70 ... 0x7f: good_rev = 0x08701033; break;
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case 0xa0 ... 0xaf: good_rev = 0x08a00009; break;
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default:
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return false;
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}
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if (boot_cpu_data.microcode < good_rev)
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return false;
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return true;
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}
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static const struct x86_cpu_id amd_zenbleed_microcode[] = {
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ZEN_MODEL_STEP_UCODE(0x17, 0x31, 0x0, 0x0830107b),
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ZEN_MODEL_STEP_UCODE(0x17, 0x60, 0x1, 0x0860010c),
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ZEN_MODEL_STEP_UCODE(0x17, 0x68, 0x1, 0x08608107),
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ZEN_MODEL_STEP_UCODE(0x17, 0x71, 0x0, 0x08701033),
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ZEN_MODEL_STEP_UCODE(0x17, 0xa0, 0x0, 0x08a00009),
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{}
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};
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static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
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{
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@ -980,7 +968,7 @@ static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
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if (!cpu_has(c, X86_FEATURE_AVX))
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return;
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if (!cpu_has_zenbleed_microcode()) {
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if (!x86_match_min_microcode_rev(amd_zenbleed_microcode)) {
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pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
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msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
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} else {
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@ -1063,12 +1051,6 @@ static void init_amd(struct cpuinfo_x86 *c)
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early_init_amd(c);
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_cpu_cap(c, 0*32+31);
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if (c->x86 >= 0x10)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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@ -119,12 +119,6 @@ static void init_centaur(struct cpuinfo_x86 *c)
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u32 fcr_clr = 0;
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u32 lo, hi, newlo;
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u32 aa, bb, cc, dd;
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_cpu_cap(c, 0*32+31);
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#endif
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early_init_centaur(c);
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init_intel_cacheinfo(c);
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@ -195,12 +195,6 @@ static void init_cyrix(struct cpuinfo_x86 *c)
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char *buf = c->x86_model_id;
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const char *p = NULL;
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_cpu_cap(c, 0*32+31);
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/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
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if (test_cpu_cap(c, 1*32+24)) {
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clear_cpu_cap(c, 1*32+24);
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@ -174,12 +174,6 @@ static void init_hygon(struct cpuinfo_x86 *c)
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early_init_hygon(c);
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_cpu_cap(c, 0*32+31);
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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/*
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