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KVM: arm64: Rely on visibility to let PIR*_ELx/TCR2_ELx UNDEF

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With a visibility defined for these registers, there is no need
to check again for S1PIE or TCRX being implemented as perform_access()
already handles it.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241023145345.1613824-27-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
This commit is contained in:
Marc Zyngier 2024-10-23 15:53:34 +01:00 committed by Oliver Upton
parent a68cddbe47
commit b482412030
1 changed files with 3 additions and 31 deletions
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34
arch/arm64/kvm/sys_regs.c
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@ -369,18 +369,6 @@ static bool access_rw(struct kvm_vcpu *vcpu,
return true;
}
static bool check_s1pie_access_rw(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
if (!kvm_has_s1pie(vcpu->kvm)) {
kvm_inject_undefined(vcpu);
return false;
}
return access_rw(vcpu, p, r);
}
/*
* See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
*/
@ -445,10 +433,6 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu,
bool was_enabled = vcpu_has_cache_enabled(vcpu);
u64 val, mask, shift;
if (reg_to_encoding(r) == SYS_TCR2_EL1 &&
!kvm_has_tcr2(vcpu->kvm))
return undef_access(vcpu, p, r);
BUG_ON(!p->is_write);
get_access_mask(r, &mask, &shift);
@ -467,18 +451,6 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu,
return true;
}
static bool access_tcr2_el2(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
if (!kvm_has_tcr2(vcpu->kvm)) {
kvm_inject_undefined(vcpu);
return false;
}
return access_rw(vcpu, p, r);
}
static bool access_actlr(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
@ -2937,7 +2909,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
EL2_REG_FILTERED(TCR2_EL2, access_tcr2_el2, reset_val, TCR2_EL2_RES1,
EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1,
tcr2_el2_visibility),
EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
@ -2966,9 +2938,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
EL2_REG_FILTERED(PIRE0_EL2, check_s1pie_access_rw, reset_val, 0,
EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0,
s1pie_el2_visibility),
EL2_REG_FILTERED(PIR_EL2, check_s1pie_access_rw, reset_val, 0,
EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0,
s1pie_el2_visibility),
EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),