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arm64: dts: qcom: sm8250: Define CPU topology
sm8250 has a big.LITTLE CPU setup with DynamIQ, so all cores are within the same CPU cluster and LLC (Last-Level Cache) domain. Define this topology to help the scheduler make decisions. Signed-off-by: Danny Lin <danny@kdrag0n.dev> Link: https://lore.kernel.org/r/20210112013255.415253-1-danny@kdrag0n.dev Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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@ -203,6 +203,42 @@ L2_700: l2-cache {
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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firmware {
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