github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-28 01:55:51 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema

Browse Source 
Convert TI irq-crossbar binding from text format to DT schema.

As part of conversion following changes are made:
 - Add '#interrupt-cells' as a required property which was missing in
   text binding
 - As irq-crossbar is interrupt-controller. Move binding from
   bindings/arm/omap to bindings/interrupt-controller

Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Link: https://patch.msgid.link/20260612-crossbar-v3-1-266747bc2e86@gmail.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Bhargav Joshi 2026-06-12 02:42:29 +05:30 committed by Rob Herring (Arm)
parent 61a7e4c2c9
commit b417b241df
2 changed files with 96 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
Documentation/devicetree/bindings/arm/omap/crossbar.txt
View File

@ -1,55 +0,0 @@
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.
Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
- interrupt-controller: indicates that this block is an interrupt controller.
- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
crossbar. These interrupt lines are reserved in the soc,
so crossbar bar driver should not consider them as free
lines.
Optional properties:
- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
crossbar. These irqs have a crossbar register, but still cannot be used.
- ti,irqs-safe-map: integer which maps to a safe configuration to use
when the interrupt controller irq is unused (when not provided, default is 0)
Examples:
crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
ti,max-irqs = <160>;
ti,max-crossbar-sources = <400>;
ti,reg-size = <2>;
ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
ti,irqs-skip = <10 133 139 140>;
};
Consumer:
========
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
further details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = <GIC_SPI request_number interrupt_level>
Example:
device_x@4a023000 {
/* Crossbar 8 used */
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
...
};

96
Documentation/devicetree/bindings/interrupt-controller/ti,irq-crossbar.yaml Normal file
View File

@ -0,0 +1,96 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ti,irq-crossbar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments IRQ Crossbar
maintainers:
- Sricharan R <r.sricharan@ti.com>
description:
Some socs have a large number of interrupts requests to service the needs of
its many peripherals and subsystems. All of the interrupt lines from the
subsystems are not needed at the same time, so they have to be muxed to the
irq-controller appropriately. In such places a interrupt controllers are
preceded by an CROSSBAR that provides flexibility in muxing the device
requests to the controller inputs.
properties:
compatible:
const: ti,irq-crossbar
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 3
ti,max-irqs:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Total number of irqs available at the parent interrupt controller.
minimum: 1
ti,max-crossbar-sources:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Maximum number of crossbar sources that can be routed.
minimum: 1
ti,reg-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Size of a individual register in bytes. Every individual
register is assumed to be of same size.
enum: [1, 2, 4]
ti,irqs-reserved:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
List of the reserved irq lines that are not muxed using crossbar. These
interrupt lines are reserved in the soc, so crossbar bar driver should not
consider them as free lines.
ti,irqs-skip:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Similar to "ti,irqs-reserved", but these are for SOC-specific hard-wiring
of those irqs which unexpectedly bypasses the crossbar. These irqs have a
crossbar register, but still cannot be used.
ti,irqs-safe-map:
$ref: /schemas/types.yaml#/definitions/uint32
description:
integer which maps to a safe configuration to use when the interrupt
controller irq is unused.
default: 0
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- ti,max-irqs
- ti,max-crossbar-sources
- ti,reg-size
- ti,irqs-reserved
additionalProperties: false
examples:
- |
crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
interrupt-controller;
#interrupt-cells = <3>;
ti,max-irqs = <160>;
ti,max-crossbar-sources = <400>;
ti,reg-size = <2>;
ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
ti,irqs-skip = <10 133 139 140>;
};