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drm/amdgpu/gfx12.1: Add ip dump support
Add support for dumping IP register state. v2: fixes suggested by Mukul Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
c52d32e6e7
commit
b3f2f83e84
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@ -69,6 +69,127 @@ MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc_1.bin");
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(SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
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(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
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static const struct amdgpu_hwip_reg_entry gc_reg_list_12_1[] = {
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SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
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SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
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SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
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SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
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SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2),
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SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),
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SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
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/* cp header registers */
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
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/* SE status registers */
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SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
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SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
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};
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static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12_1[] = {
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/* compute registers */
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
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/* cp header registers */
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
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SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
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};
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static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id);
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static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev);
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static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev);
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@ -1149,6 +1270,155 @@ static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
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return 0;
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}
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static void gfx_v12_1_alloc_ip_dump(struct amdgpu_device *adev)
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{
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uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1);
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uint32_t *ptr, inst, num_xcc;
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num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL);
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if (!ptr) {
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DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
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adev->gfx.ip_dump_core = NULL;
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} else {
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adev->gfx.ip_dump_core = ptr;
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}
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/* Allocate memory for compute queue registers for all the instances */
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reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1);
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inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
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adev->gfx.mec.num_queue_per_pipe;
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ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL);
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if (!ptr) {
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DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
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adev->gfx.ip_dump_compute_queues = NULL;
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} else {
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adev->gfx.ip_dump_compute_queues = ptr;
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}
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}
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static void gfx_v12_1_ip_print(struct amdgpu_ip_block *ip_block,
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struct drm_printer *p)
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{
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struct amdgpu_device *adev = ip_block->adev;
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uint32_t i, j, k;
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uint32_t xcc_id, xcc_offset, inst_offset;
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uint32_t num_xcc, reg, num_inst;
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uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1);
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if (!adev->gfx.ip_dump_core)
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return;
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num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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drm_printf(p, "Number of Instances:%d\n", num_xcc);
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for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
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xcc_offset = xcc_id * reg_count;
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drm_printf(p, "\nInstance id:%d\n", xcc_id);
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for (i = 0; i < reg_count; i++)
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drm_printf(p, "%-50s \t 0x%08x\n",
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gc_reg_list_12_1[i].reg_name,
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adev->gfx.ip_dump_core[xcc_offset + i]);
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}
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/* print compute queue registers for all instances */
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if (!adev->gfx.ip_dump_compute_queues)
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return;
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reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1);
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drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n",
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num_xcc,
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adev->gfx.mec.num_mec,
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adev->gfx.mec.num_pipe_per_mec,
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adev->gfx.mec.num_queue_per_pipe);
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num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
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adev->gfx.mec.num_queue_per_pipe;
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for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
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xcc_offset = xcc_id * reg_count * num_inst;
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inst_offset = 0;
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for (i = 0; i < adev->gfx.mec.num_mec; i++) {
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for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
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for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
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drm_printf(p,
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"\nxcc:%d mec:%d, pipe:%d, queue:%d\n",
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xcc_id, i, j, k);
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for (reg = 0; reg < reg_count; reg++) {
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drm_printf(p,
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"%-50s \t 0x%08x\n",
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gc_cp_reg_list_12_1[reg].reg_name,
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adev->gfx.ip_dump_compute_queues
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[xcc_offset + inst_offset +
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reg]);
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}
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inst_offset += reg_count;
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}
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}
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}
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}
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}
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static void gfx_v12_1_ip_dump(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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uint32_t i, j, k;
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uint32_t num_xcc, reg, num_inst;
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uint32_t xcc_id, xcc_offset, inst_offset;
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uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1);
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if (!adev->gfx.ip_dump_core)
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return;
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num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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amdgpu_gfx_off_ctrl(adev, false);
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for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
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xcc_offset = xcc_id * reg_count;
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for (i = 0; i < reg_count; i++)
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adev->gfx.ip_dump_core[xcc_offset + i] =
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RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_12_1[i],
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GET_INST(GC, xcc_id)));
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}
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amdgpu_gfx_off_ctrl(adev, true);
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/* dump compute queue registers for all instances */
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if (!adev->gfx.ip_dump_compute_queues)
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return;
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num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
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adev->gfx.mec.num_queue_per_pipe;
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reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1);
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amdgpu_gfx_off_ctrl(adev, false);
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mutex_lock(&adev->srbm_mutex);
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for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
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xcc_offset = xcc_id * reg_count * num_inst;
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inst_offset = 0;
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for (i = 0; i < adev->gfx.mec.num_mec; i++) {
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for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
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for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
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/* ME0 is for GFX so start from 1 for CP */
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soc_v1_0_grbm_select(adev, 1 + i, j, k, 0,
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GET_INST(GC, xcc_id));
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for (reg = 0; reg < reg_count; reg++) {
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adev->gfx.ip_dump_compute_queues
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[xcc_offset +
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inst_offset + reg] =
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RREG32(SOC15_REG_ENTRY_OFFSET_INST(
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gc_cp_reg_list_12_1[reg],
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GET_INST(GC, xcc_id)));
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}
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inst_offset += reg_count;
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}
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}
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}
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}
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soc_v1_0_grbm_select(adev, 0, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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amdgpu_gfx_off_ctrl(adev, true);
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}
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static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block)
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{
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uint16_t major_ver, minor_ver;
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@ -1287,6 +1557,8 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block)
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if (r)
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return r;
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gfx_v12_1_alloc_ip_dump(adev);
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mutex_init(&adev->gfx.mec.reset_mutex);
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return 0;
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@ -1326,6 +1598,9 @@ static int gfx_v12_1_sw_fini(struct amdgpu_ip_block *ip_block)
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gfx_v12_1_free_microcode(adev);
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amdgpu_gfx_sysfs_fini(adev);
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kfree(adev->gfx.ip_dump_core);
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kfree(adev->gfx.ip_dump_compute_queues);
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return 0;
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}
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@ -3912,6 +4187,8 @@ static const struct amd_ip_funcs gfx_v12_1_ip_funcs = {
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.set_clockgating_state = gfx_v12_1_set_clockgating_state,
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.set_powergating_state = gfx_v12_1_set_powergating_state,
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.get_clockgating_state = gfx_v12_1_get_clockgating_state,
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.dump_ip_state = gfx_v12_1_ip_dump,
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.print_ip_state = gfx_v12_1_ip_print,
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};
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static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_compute = {
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Reference in New Issue
Block a user