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KVM VMX changes for 6.4:
- Fix a bug in emulation of ENCLS in compatibility mode - Allow emulation of NOP and PAUSE for L2 - Misc cleanups -----BEGIN PGP SIGNATURE----- iQJGBAABCgAwFiEEMHr+pfEFOIzK+KY1YJEiAU0MEvkFAmRGuYgSHHNlYW5qY0Bn b29nbGUuY29tAAoJEGCRIgFNDBL5kQUP/jV5Q8ZeVCzlf6ZCeAHnWX/Hahsv6i6H ooNL8W6p8FI5xlYOWh8J02JpmLUrNWURCPqvr0oYLm4r1UlJ/OGjyuKB8d7SZ7z/ RaLN7tppMod527J+Qm3ptHQbTKAGHe4dEoiX46cuvTEcCxrsVykYltvfD1rNuSQA VcaNJkkcHv/KuItUHLAuntCAiFvbD1gYNLfUAC7e0htGjLRLxg3+ugHEiFcJ3c6y z4ged1toYLGD962jWSIgokFbivfUNZT25WlZjBliMa/E8+ckTAzmc67UJYvhNBOM HyAHs0hp+XtSgfcCgNkI+WDrFXXgxa+QQcMFvRWacS3Hx6tgJoQ51FRMevmumn0O zBPk3+BOquhknqb5NbmwRZoLExffo+86fFlDcgszzvV4Y/vBfp/XTsuJZCnaiMDZ wdmJoF4mhRDtgt7yORltpjHqp3yRmLqMNUb3sxXLRA9D+edo9mr8SXujOnukmXoH o/ZpEollTPUQ7od/uDIvDyosWvb65IbYwsKGdOanfBacVrxy5OPM38mPF7u9AyzD Gn81H/OhwhpTSBAX7kLMGeK/QGkyIBEUM1levdmcAk0nKYQzHzsI7tMYfqwXuQSu qKAcF+qtpOReWmb4KaJZ7c0HQIBQHOKQ6exXxnQJuLjnAHS0674NxMDkT5a1EGRL Q9OPSTSYBMDC =FOnk -----END PGP SIGNATURE----- Merge tag 'kvm-x86-vmx-6.4' of https://github.com/kvm-x86/linux into HEAD KVM VMX changes for 6.4: - Fix a bug in emulation of ENCLS in compatibility mode - Allow emulation of NOP and PAUSE for L2 - Misc cleanups
This commit is contained in:
Paolo Bonzini
commit
b3c98052d4
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@ -6756,36 +6756,9 @@ static u64 nested_vmx_calc_vmcs_enum_msr(void)
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return (u64)max_idx << VMCS_FIELD_INDEX_SHIFT;
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}
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/*
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* nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
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* returned for the various VMX controls MSRs when nested VMX is enabled.
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* The same values should also be used to verify that vmcs12 control fields are
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* valid during nested entry from L1 to L2.
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* Each of these control msrs has a low and high 32-bit half: A low bit is on
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* if the corresponding bit in the (32-bit) control field *must* be on, and a
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* bit in the high half is on if the corresponding bit in the control field
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* may be on. See also vmx_control_verify().
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*/
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void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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static void nested_vmx_setup_pinbased_ctls(struct vmcs_config *vmcs_conf,
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struct nested_vmx_msrs *msrs)
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{
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struct nested_vmx_msrs *msrs = &vmcs_conf->nested;
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/*
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* Note that as a general rule, the high half of the MSRs (bits in
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* the control fields which may be 1) should be initialized by the
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* intersection of the underlying hardware's MSR (i.e., features which
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* can be supported) and the list of features we want to expose -
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* because they are known to be properly supported in our code.
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* Also, usually, the low half of the MSRs (bits which must be 1) can
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* be set to 0, meaning that L1 may turn off any of these bits. The
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* reason is that if one of these bits is necessary, it will appear
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* in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
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* fields of vmcs01 and vmcs02, will turn these bits off - and
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* nested_vmx_l1_wants_exit() will not pass related exits to L1.
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* These rules have exceptions below.
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*/
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/* pin-based controls */
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msrs->pinbased_ctls_low =
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PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
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@ -6798,8 +6771,11 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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msrs->pinbased_ctls_high |=
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PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
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PIN_BASED_VMX_PREEMPTION_TIMER;
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}
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/* exit controls */
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static void nested_vmx_setup_exit_ctls(struct vmcs_config *vmcs_conf,
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struct nested_vmx_msrs *msrs)
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{
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msrs->exit_ctls_low =
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VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
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@ -6818,8 +6794,11 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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/* We support free control of debug control saving. */
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msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
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}
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/* entry controls */
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static void nested_vmx_setup_entry_ctls(struct vmcs_config *vmcs_conf,
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struct nested_vmx_msrs *msrs)
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{
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msrs->entry_ctls_low =
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VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
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@ -6835,8 +6814,11 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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/* We support free control of debug control loading. */
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msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
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}
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/* cpu-based controls */
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static void nested_vmx_setup_cpubased_ctls(struct vmcs_config *vmcs_conf,
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struct nested_vmx_msrs *msrs)
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{
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msrs->procbased_ctls_low =
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CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
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@ -6868,12 +6850,12 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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/* We support free control of CR3 access interception. */
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msrs->procbased_ctls_low &=
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~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
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}
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/*
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* secondary cpu-based controls. Do not include those that
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* depend on CPUID bits, they are added later by
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* vmx_vcpu_after_set_cpuid.
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*/
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static void nested_vmx_setup_secondary_ctls(u32 ept_caps,
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struct vmcs_config *vmcs_conf,
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struct nested_vmx_msrs *msrs)
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{
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msrs->secondary_ctls_low = 0;
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msrs->secondary_ctls_high = vmcs_conf->cpu_based_2nd_exec_ctrl;
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@ -6951,8 +6933,11 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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if (enable_sgx)
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msrs->secondary_ctls_high |= SECONDARY_EXEC_ENCLS_EXITING;
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}
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/* miscellaneous data */
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static void nested_vmx_setup_misc_data(struct vmcs_config *vmcs_conf,
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struct nested_vmx_msrs *msrs)
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{
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msrs->misc_low = (u32)vmcs_conf->misc & VMX_MISC_SAVE_EFER_LMA;
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msrs->misc_low |=
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MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
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@ -6960,7 +6945,10 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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VMX_MISC_ACTIVITY_HLT |
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VMX_MISC_ACTIVITY_WAIT_SIPI;
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msrs->misc_high = 0;
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}
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static void nested_vmx_setup_basic(struct nested_vmx_msrs *msrs)
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{
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/*
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* This MSR reports some information about VMX support. We
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* should return information about the VMX we emulate for the
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@ -6975,7 +6963,10 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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if (cpu_has_vmx_basic_inout())
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msrs->basic |= VMX_BASIC_INOUT;
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}
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static void nested_vmx_setup_cr_fixed(struct nested_vmx_msrs *msrs)
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{
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/*
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* These MSRs specify bits which the guest must keep fixed on
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* while L1 is in VMXON mode (in L1's root mode, or running an L2).
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@ -6992,6 +6983,51 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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if (vmx_umip_emulated())
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msrs->cr4_fixed1 |= X86_CR4_UMIP;
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}
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/*
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* nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
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* returned for the various VMX controls MSRs when nested VMX is enabled.
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* The same values should also be used to verify that vmcs12 control fields are
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* valid during nested entry from L1 to L2.
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* Each of these control msrs has a low and high 32-bit half: A low bit is on
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* if the corresponding bit in the (32-bit) control field *must* be on, and a
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* bit in the high half is on if the corresponding bit in the control field
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* may be on. See also vmx_control_verify().
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*/
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void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
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{
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struct nested_vmx_msrs *msrs = &vmcs_conf->nested;
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/*
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* Note that as a general rule, the high half of the MSRs (bits in
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* the control fields which may be 1) should be initialized by the
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* intersection of the underlying hardware's MSR (i.e., features which
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* can be supported) and the list of features we want to expose -
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* because they are known to be properly supported in our code.
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* Also, usually, the low half of the MSRs (bits which must be 1) can
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* be set to 0, meaning that L1 may turn off any of these bits. The
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* reason is that if one of these bits is necessary, it will appear
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* in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
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* fields of vmcs01 and vmcs02, will turn these bits off - and
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* nested_vmx_l1_wants_exit() will not pass related exits to L1.
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* These rules have exceptions below.
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*/
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nested_vmx_setup_pinbased_ctls(vmcs_conf, msrs);
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nested_vmx_setup_exit_ctls(vmcs_conf, msrs);
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nested_vmx_setup_entry_ctls(vmcs_conf, msrs);
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nested_vmx_setup_cpubased_ctls(vmcs_conf, msrs);
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nested_vmx_setup_secondary_ctls(ept_caps, vmcs_conf, msrs);
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nested_vmx_setup_misc_data(vmcs_conf, msrs);
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nested_vmx_setup_basic(msrs);
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nested_vmx_setup_cr_fixed(msrs);
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msrs->vmcs_enum = nested_vmx_calc_vmcs_enum_msr();
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}
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@ -29,14 +29,14 @@ static int sgx_get_encls_gva(struct kvm_vcpu *vcpu, unsigned long offset,
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/* Skip vmcs.GUEST_DS retrieval for 64-bit mode to avoid VMREADs. */
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*gva = offset;
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if (!is_long_mode(vcpu)) {
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if (!is_64_bit_mode(vcpu)) {
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vmx_get_segment(vcpu, &s, VCPU_SREG_DS);
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*gva += s.base;
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}
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if (!IS_ALIGNED(*gva, alignment)) {
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fault = true;
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} else if (likely(is_long_mode(vcpu))) {
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} else if (likely(is_64_bit_mode(vcpu))) {
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fault = is_noncanonical_address(*gva, vcpu);
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} else {
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*gva &= 0xffffffff;
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@ -7900,6 +7900,21 @@ static int vmx_check_intercept(struct kvm_vcpu *vcpu,
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/* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
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break;
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case x86_intercept_pause:
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/*
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* PAUSE is a single-byte NOP with a REPE prefix, i.e. collides
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* with vanilla NOPs in the emulator. Apply the interception
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* check only to actual PAUSE instructions. Don't check
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* PAUSE-loop-exiting, software can't expect a given PAUSE to
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* exit, i.e. KVM is within its rights to allow L2 to execute
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* the PAUSE.
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*/
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if ((info->rep_prefix != REPE_PREFIX) ||
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!nested_cpu_has2(vmcs12, CPU_BASED_PAUSE_EXITING))
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return X86EMUL_CONTINUE;
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break;
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/* TODO: check more intercepts... */
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default:
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break;
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