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Qualcomm ARM32 DeviceTree changes for v6.9

Browse Source 
Support for the Samsung Galaxy Tab 4 10.1 LTE is added.
 
 On MSM8226 CPU, SAW and ACC nodes are introduced to enable SMP support.
 Watchdog definition is also added, and all nodes are sorted and cleaned
 up.
 rmtfs memory is defined on HTC One Mini 2, vibrator support is addedto
 LG G Watch R, touch keycodes are defined for Samsung Galaxy Tab 4.
 The Samsung Galaxy Tab 4 DeviceTree is refactored to allow more variants
 to be introduced easily.
 
 The SAW nodes across APQ8064, IPQ8064, MSM8960 and MSM8974 are updated
 based on recent work on the binding and driver.
 
 On IPQ8064 SAW nodes are cleaned up, and unused reset-names is dropped
 from DWC3.
 
 On MSM8960 GSBI3 and the I2C bus therein is introduced, in order to
 introduce touchscreen support on the Samsung Galaxy Express SGH-I437.
 gpio-keys are introduced on the same.
 
 On MSM8974 the QFPROM register size is corrected. The order of the
 clocks in the SDX65 DWC3 node is corrected to match the binding.
 
 For a variety of platforms interrupt-related constants are replaced
 with defined.
 
 The mach-qcom Kconfig options are cleaned up, to avoid unnecessary
 per-platform options.
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Merge tag 'qcom-arm32-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm ARM32 DeviceTree changes for v6.9

Support for the Samsung Galaxy Tab 4 10.1 LTE is added.

On MSM8226 CPU, SAW and ACC nodes are introduced to enable SMP support.
Watchdog definition is also added, and all nodes are sorted and cleaned
up.
rmtfs memory is defined on HTC One Mini 2, vibrator support is addedto
LG G Watch R, touch keycodes are defined for Samsung Galaxy Tab 4.
The Samsung Galaxy Tab 4 DeviceTree is refactored to allow more variants
to be introduced easily.

The SAW nodes across APQ8064, IPQ8064, MSM8960 and MSM8974 are updated
based on recent work on the binding and driver.

On IPQ8064 SAW nodes are cleaned up, and unused reset-names is dropped
from DWC3.

On MSM8960 GSBI3 and the I2C bus therein is introduced, in order to
introduce touchscreen support on the Samsung Galaxy Express SGH-I437.
gpio-keys are introduced on the same.

On MSM8974 the QFPROM register size is corrected. The order of the
clocks in the SDX65 DWC3 node is corrected to match the binding.

For a variety of platforms interrupt-related constants are replaced
with defined.

The mach-qcom Kconfig options are cleaned up, to avoid unnecessary
per-platform options.

* tag 'qcom-arm32-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (40 commits)
  ARM: dts: qcom: samsung-matisse-common: Add UART
  ARM: dts: qcom: Add support for Samsung Galaxy Tab 4 10.1 LTE (SM-T535)
  ARM: dts: qcom: samsung-matisse-common: Add initial common device tree
  ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices
  ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices
  ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device
  ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device
  ARM: dts: qcom: msm8960: declare SAW2 regulators
  ARM: dts: qcom: apq8064: declare SAW2 regulators
  ARM: dts: qcom: ipq8064: rename SAW nodes to power-manager
  ARM: dts: qcom: ipq4019: rename SAW nodes to power-manager
  ARM: dts: qcom: msm8974: rename SAW nodes to power-manager
  ARM: dts: qcom: msm8960: rename SAW nodes to power-manager
  ARM: dts: qcom: apq8084: rename SAW nodes to power-manager
  ARM: dts: qcom: apq8064: rename SAW nodes to power-manager
  ARM: dts: qcom: ipq8064: use SoC-specific compatibles for SAW2 devices
  ARM: dts: qcom: ipq4019: use SoC-specific compatibles for SAW2 devices
  ARM: dts: qcom: msm8960: use SoC-specific compatibles for SAW2 devices
  ARM: dts: qcom: msm8974: use new compat string for L2 SAW2 unit
  ARM: dts: qcom: apq8084: use new compat string for L2 SAW2 unit
  ...

Link: https://lore.kernel.org/r/20240304033507.89751-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-04 08:38:47 +01:00
commit b3c6f1ff32
22 changed files with 1325 additions and 1004 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/Makefile
View File

@ -158,9 +158,7 @@ textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
ifeq ($(CONFIG_ARCH_SA1100),y)
textofs-$(CONFIG_SA1111) := 0x00208000
endif
textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
textofs-$(CONFIG_ARCH_QCOM_RESERVE_SMEM) := 0x00208000
textofs-$(CONFIG_ARCH_MESON) := 0x00208000
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000

1
arch/arm/boot/dts/qcom/Makefile
View File

@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-msm8926-microsoft-superman-lte.dtb \
qcom-msm8926-microsoft-tesla.dtb \
qcom-msm8926-motorola-peregrine.dtb \
qcom-msm8926-samsung-matisselte.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8960-samsung-expressatt.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \

38
arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts
View File

@ -7,6 +7,7 @@
#include "qcom-msm8226.dtsi"
#include "pm8226.dtsi"
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
/delete-node/ &adsp_region;
@ -56,6 +57,29 @@ vreg_wlan: wlan-regulator {
pinctrl-names = "default";
pinctrl-0 = <&wlan_regulator_default_state>;
};
pwm_vibrator: pwm {
compatible = "clk-pwm";
clocks = <&mmcc CAMSS_GP0_CLK>;
pinctrl-0 = <&vibrator_clk_default_state>;
pinctrl-names = "default";
#pwm-cells = <2>;
};
vibrator {
compatible = "pwm-vibrator";
pwms = <&pwm_vibrator 0 10000>;
pwm-names = "enable";
vcc-supply = <&pm8226_l28>;
enable-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&vibrator_en_default_state>;
pinctrl-names = "default";
};
};
&adsp {
@ -330,6 +354,20 @@ reset-pins {
};
};
vibrator_clk_default_state: vibrator-clk-default-state {
pins = "gpio33";
function = "gp0_clk";
drive-strength = <2>;
bias-disable;
};
vibrator_en_default_state: vibrator-en-default-state {
pins = "gpio62";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wlan_hostwake_default_state: wlan-hostwake-default-state {
pins = "gpio37";
function = "gpio";

452
arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts
View File

@ -5,142 +5,13 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "qcom-msm8226.dtsi"
#include "pm8226.dtsi"
/delete-node/ &adsp_region;
/delete-node/ &smem_region;
#include "qcom-msm8226-samsung-matisse-common.dtsi"
/ {
model = "Samsung Galaxy Tab 4 10.1";
compatible = "samsung,matisse-wifi", "qcom,apq8026";
chassis-type = "tablet";
aliases {
mmc0 = &sdhc_1; /* SDC1 eMMC slot */
mmc1 = &sdhc_2; /* SDC2 SD card slot */
display0 = &framebuffer0;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "display0";
framebuffer0: framebuffer@3200000 {
compatible = "simple-framebuffer";
reg = <0x03200000 0x800000>;
width = <1280>;
height = <800>;
stride = <(1280 * 3)>;
format = "r8g8b8";
};
};
gpio-hall-sensor {
compatible = "gpio-keys";
event-hall-sensor {
label = "Hall Effect Sensor";
gpios = <&tlmm 110 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
key-home {
label = "Home";
gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOMEPAGE>;
debounce-interval = <15>;
};
key-volume-down {
label = "Volume Down";
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <15>;
};
key-volume-up {
label = "Volume Up";
gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <15>;
};
};
i2c-backlight {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
pinctrl-0 = <&backlight_i2c_default_state>;
pinctrl-names = "default";
i2c-gpio,delay-us = <4>;
#address-cells = <1>;
#size-cells = <0>;
backlight@2c {
compatible = "ti,lp8556";
reg = <0x2c>;
dev-ctrl = /bits/ 8 <0x80>;
init-brt = /bits/ 8 <0x3f>;
pwms = <&backlight_pwm 0 100000>;
pwm-names = "lp8556";
rom-a0h {
rom-addr = /bits/ 8 <0xa0>;
rom-val = /bits/ 8 <0x44>;
};
rom-a1h {
rom-addr = /bits/ 8 <0xa1>;
rom-val = /bits/ 8 <0x6c>;
};
rom-a5h {
rom-addr = /bits/ 8 <0xa5>;
rom-val = /bits/ 8 <0x24>;
};
};
};
backlight_pwm: pwm {
compatible = "clk-pwm";
#pwm-cells = <2>;
clocks = <&mmcc CAMSS_GP0_CLK>;
pinctrl-0 = <&backlight_pwm_default_state>;
pinctrl-names = "default";
};
reg_tsp_1p8v: regulator-tsp-1p8v {
compatible = "regulator-fixed";
regulator-name = "tsp_1p8v";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&tsp_en_default_state>;
};
reg_tsp_3p3v: regulator-tsp-3p3v {
compatible = "regulator-fixed";
regulator-name = "tsp_3p3v";
@ -153,74 +24,6 @@ reg_tsp_3p3v: regulator-tsp-3p3v {
pinctrl-names = "default";
pinctrl-0 = <&tsp_en1_default_state>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
framebuffer@3200000 {
reg = <0x03200000 0x800000>;
no-map;
};
mpss@8400000 {
reg = <0x08400000 0x1f00000>;
no-map;
};
mba@a300000 {
reg = <0x0a300000 0x100000>;
no-map;
};
reserved@cb00000 {
reg = <0x0cb00000 0x700000>;
no-map;
};
wcnss@d200000 {
reg = <0x0d200000 0x700000>;
no-map;
};
adsp_region: adsp@d900000 {
reg = <0x0d900000 0x1800000>;
no-map;
};
venus@f100000 {
reg = <0x0f100000 0x500000>;
no-map;
};
smem_region: smem@fa00000 {
reg = <0x0fa00000 0x100000>;
no-map;
};
reserved@fb00000 {
reg = <0x0fb00000 0x260000>;
no-map;
};
rfsa@fd60000 {
reg = <0x0fd60000 0x20000>;
no-map;
};
rmtfs@fd80000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0fd80000 0x180000>;
no-map;
qcom,client-id = <1>;
};
};
};
&adsp {
status = "okay";
};
&blsp1_i2c2 {
@ -243,21 +46,6 @@ accelerometer@1d {
};
};
&blsp1_i2c4 {
status = "okay";
muic: usb-switch@25 {
compatible = "siliconmitus,sm5502-muic";
reg = <0x25>;
interrupt-parent = <&tlmm>;
interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&muic_int_default_state>;
};
};
&blsp1_i2c5 {
status = "okay";
@ -268,6 +56,13 @@ touchscreen@4a {
interrupt-parent = <&tlmm>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
linux,keycodes = <KEY_RESERVED>,
<KEY_RESERVED>,
<KEY_RESERVED>,
<KEY_RESERVED>,
<KEY_APPSELECT>,
<KEY_BACK>;
pinctrl-names = "default";
pinctrl-0 = <&tsp_int_rst_default_state>;
@ -278,242 +73,19 @@ touchscreen@4a {
};
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm8226-regulators";
pm8226_s3: s3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
};
pm8226_s4: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8226_s5: s5 {
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
};
pm8226_l1: l1 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
pm8226_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8226_l3: l3 {
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1337500>;
regulator-always-on;
};
pm8226_l4: l4 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8226_l5: l5 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8226_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
pm8226_l7: l7 {
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1850000>;
};
pm8226_l8: l8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
pm8226_l9: l9 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
pm8226_l10: l10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8226_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8226_l14: l14 {
regulator-min-microvolt = <2750000>;
regulator-max-microvolt = <2750000>;
};
pm8226_l15: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8226_l16: l16 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3350000>;
};
pm8226_l17: l17 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-system-load = <200000>;
regulator-allow-set-load;
regulator-always-on;
};
pm8226_l18: l18 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
};
pm8226_l19: l19 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3000000>;
};
pm8226_l20: l20 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
pm8226_l21: l21 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8226_l22: l22 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
pm8226_l23: l23 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8226_l24: l24 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1350000>;
};
pm8226_l25: l25 {
regulator-min-microvolt = <1775000>;
regulator-max-microvolt = <2125000>;
};
pm8226_l26: l26 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1300000>;
};
pm8226_l27: l27 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8226_l28: l28 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8226_lvs1: lvs1 {};
};
&pm8226_l3 {
regulator-max-microvolt = <1337500>;
};
&sdhc_1 {
vmmc-supply = <&pm8226_l17>;
vqmmc-supply = <&pm8226_l6>;
bus-width = <8>;
non-removable;
status = "okay";
};
&sdhc_2 {
vmmc-supply = <&pm8226_l18>;
vqmmc-supply = <&pm8226_l21>;
bus-width = <4>;
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
status = "okay";
&pm8226_s4 {
regulator-max-microvolt = <1800000>;
};
&tlmm {
accel_int_default_state: accel-int-default-state {
pins = "gpio54";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
backlight_i2c_default_state: backlight-i2c-default-state {
pins = "gpio20", "gpio21";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
backlight_pwm_default_state: backlight-pwm-default-state {
pins = "gpio33";
function = "gp0_clk";
};
muic_int_default_state: muic-int-default-state {
pins = "gpio67";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_en_default_state: tsp-en-default-state {
pins = "gpio31";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_en1_default_state: tsp-en1-default-state {
pins = "gpio73";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_int_rst_default_state: tsp-int-rst-default-state {
pins = "gpio17";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
};
&usb {
extcon = <&muic>, <&muic>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic>;
v1p8-supply = <&pm8226_l10>;
v3p3-supply = <&pm8226_l20>;
};

70
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
View File

@ -190,7 +190,7 @@ cpu_crit3: trip1 {
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <1 10 0x304>;
interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
@ -244,7 +244,7 @@ apps_smsm: apps@0 {
modem_smsm: modem@1 {
reg = <1>;
interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
@ -252,7 +252,7 @@ modem_smsm: modem@1 {
q6_smsm: q6@2 {
reg = <2>;
interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
@ -260,7 +260,7 @@ q6_smsm: q6@2 {
wcnss_smsm: wcnss@3 {
reg = <3>;
interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
@ -268,7 +268,7 @@ wcnss_smsm: wcnss@3 {
dsps_smsm: dsps@4 {
reg = <4>;
interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
@ -299,7 +299,7 @@ tlmm_pinmux: pinctrl@800000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ps_hold>;
@ -321,9 +321,9 @@ intc: interrupt-controller@2000000 {
timer@200a000 {
compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
"qcom,msm-timer";
interrupts = <1 1 0x301>,
<1 2 0x301>,
<1 3 0x301>;
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
clock-frequency = <27000000>;
cpu-offset = <0x80000>;
@ -365,28 +365,44 @@ acc3: clock-controller@20b8000 {
#clock-cells = <0>;
};
saw0: power-controller@2089000 {
saw0: power-manager@2089000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
saw0_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
saw1: power-controller@2099000 {
saw1: power-manager@2099000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
saw1_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
saw2: power-controller@20a9000 {
saw2: power-manager@20a9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
regulator;
saw2_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
saw3: power-controller@20b9000 {
saw3: power-manager@20b9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
regulator;
saw3_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
sps_sic_non_secure: sps-sic-non-secure@12100000 {
@ -411,7 +427,7 @@ gsbi1_serial: serial@12450000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12450000 0x100>,
<0x12400000 0x03>;
interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@ -423,7 +439,7 @@ gsbi1_i2c: i2c@12460000 {
pinctrl-1 = <&i2c1_pins_sleep>;
pinctrl-names = "default", "sleep";
reg = <0x12460000 0x1000>;
interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
@ -452,7 +468,7 @@ gsbi2_i2c: i2c@124a0000 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_pins_sleep>;
pinctrl-names = "default", "sleep";
interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
@ -539,7 +555,7 @@ gsbi5_serial: serial@1a240000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x100>,
<0x1a200000 0x03>;
interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@ -548,7 +564,7 @@ gsbi5_serial: serial@1a240000 {
gsbi5_spi: spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi5_default>;
pinctrl-1 = <&spi5_sleep>;
pinctrl-names = "default", "sleep";
@ -575,7 +591,7 @@ gsbi6_serial: serial@16540000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16540000 0x100>,
<0x16500000 0x03>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@ -611,7 +627,7 @@ gsbi7_serial: serial@16640000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16640000 0x1000>,
<0x16600000 0x1000>;
interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@ -908,7 +924,7 @@ sdcc3: mmc@12180000 {
sdcc3bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@ -936,7 +952,7 @@ sdcc4: mmc@121c0000 {
sdcc4bam: dma-controller@121c2000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x121c2000 0x8000>;
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC4_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@ -965,7 +981,7 @@ sdcc1: mmc@12400000 {
sdcc1bam: dma-controller@12402000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;

13
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
View File

@ -629,30 +629,29 @@ frame@f9028000 {
};
};
saw0: power-controller@f9089000 {
saw0: power-manager@f9089000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
};
saw1: power-controller@f9099000 {
saw1: power-manager@f9099000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
};
saw2: power-controller@f90a9000 {
saw2: power-manager@f90a9000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
};
saw3: power-controller@f90b9000 {
saw3: power-manager@f90b9000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
};
saw_l2: power-controller@f9012000 {
compatible = "qcom,saw2";
saw_l2: power-manager@f9012000 {
compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
regulator;
};
acc0: power-manager@f9088000 {

146
arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi
View File

@ -27,87 +27,83 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
};
soc {
rng@22000 {
status = "okay";
&prng {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
pinctrl@1000000 {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
};
pinmux_cs {
function = "gpio";
pins = "gpio54";
};
pinconf {
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
};
blsp_dma: dma-controller@7884000 {
status = "okay";
pinmux_cs {
function = "gpio";
pins = "gpio54";
};
spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
mx25l25635e@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "mx25l25635e";
spi-max-frequency = <24000000>;
};
pinconf {
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
serial@78af000 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
cryptobam: dma-controller@8e04000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
wifi@a000000 {
status = "okay";
};
wifi@a800000 {
status = "okay";
pinconf_cs {
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
};

35
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
View File

@ -162,10 +162,10 @@ scm {
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <48000000>;
always-on;
};
@ -350,34 +350,29 @@ acc3: power-manager@b0b8000 {
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
saw0: regulator@b089000 {
compatible = "qcom,saw2";
saw0: power-manager@b089000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw1: regulator@b099000 {
compatible = "qcom,saw2";
saw1: power-manager@b099000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw2: regulator@b0a9000 {
compatible = "qcom,saw2";
saw2: power-manager@b0a9000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw3: regulator@b0b9000 {
compatible = "qcom,saw2";
saw3: power-manager@b0b9000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw_l2: regulator@b012000 {
compatible = "qcom,saw2";
saw_l2: power-manager@b012000 {
compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2";
reg = <0xb012000 0x1000>;
regulator;
};
blsp1_uart1: serial@78af000 {
@ -684,7 +679,7 @@ usb2: usb@60f8800 {
clocks = <&gcc GCC_USB2_MASTER_CLK>,
<&gcc GCC_USB2_SLEEP_CLK>,
<&gcc GCC_USB2_MOCK_UTMI_CLK>;
clock-names = "master", "sleep", "mock_utmi";
clock-names = "core", "sleep", "mock_utmi";
ranges;
status = "disabled";

12
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
View File

@ -586,10 +586,9 @@ acc0: clock-controller@2088000 {
#clock-cells = <0>;
};
saw0: regulator@2089000 {
compatible = "qcom,saw2";
saw0: power-manager@2089000 {
compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
acc1: clock-controller@2098000 {
@ -601,10 +600,9 @@ acc1: clock-controller@2098000 {
#clock-cells = <0>;
};
saw1: regulator@2099000 {
compatible = "qcom,saw2";
saw1: power-manager@2099000 {
compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
nss_common: syscon@3000000 {
@ -623,7 +621,6 @@ usb3_0: usb@100f8800 {
ranges;
resets = <&gcc USB30_0_MASTER_RESET>;
reset-names = "master";
status = "disabled";
@ -669,7 +666,6 @@ usb3_1: usb@110f8800 {
ranges;
resets = <&gcc USB30_1_MASTER_RESET>;
reset-names = "master";
status = "disabled";

457
arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi Normal file
View File

@ -0,0 +1,457 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com>
*/
#include <dt-bindings/input/input.h>
#include "qcom-msm8226.dtsi"
#include "pm8226.dtsi"
/delete-node/ &adsp_region;
/delete-node/ &smem_region;
/ {
aliases {
mmc0 = &sdhc_1; /* SDC1 eMMC slot */
mmc1 = &sdhc_2; /* SDC2 SD card slot */
display0 = &framebuffer0;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
stdout-path = "display0";
framebuffer0: framebuffer@3200000 {
compatible = "simple-framebuffer";
reg = <0x03200000 0x800000>;
width = <1280>;
height = <800>;
stride = <(1280 * 3)>;
format = "r8g8b8";
};
};
gpio-hall-sensor {
compatible = "gpio-keys";
event-hall-sensor {
label = "Hall Effect Sensor";
gpios = <&tlmm 110 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
key-home {
label = "Home";
gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOMEPAGE>;
debounce-interval = <15>;
};
key-volume-down {
label = "Volume Down";
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <15>;
};
key-volume-up {
label = "Volume Up";
gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <15>;
};
};
i2c-backlight {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
pinctrl-0 = <&backlight_i2c_default_state>;
pinctrl-names = "default";
i2c-gpio,delay-us = <4>;
#address-cells = <1>;
#size-cells = <0>;
backlight@2c {
compatible = "ti,lp8556";
reg = <0x2c>;
dev-ctrl = /bits/ 8 <0x80>;
init-brt = /bits/ 8 <0x3f>;
pwms = <&backlight_pwm 0 100000>;
pwm-names = "lp8556";
rom-a0h {
rom-addr = /bits/ 8 <0xa0>;
rom-val = /bits/ 8 <0x44>;
};
rom-a1h {
rom-addr = /bits/ 8 <0xa1>;
rom-val = /bits/ 8 <0x6c>;
};
rom-a5h {
rom-addr = /bits/ 8 <0xa5>;
rom-val = /bits/ 8 <0x24>;
};
};
};
backlight_pwm: pwm {
compatible = "clk-pwm";
#pwm-cells = <2>;
clocks = <&mmcc CAMSS_GP0_CLK>;
pinctrl-0 = <&backlight_pwm_default_state>;
pinctrl-names = "default";
};
reg_tsp_1p8v: regulator-tsp-1p8v {
compatible = "regulator-fixed";
regulator-name = "tsp_1p8v";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&tsp_en_default_state>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
framebuffer@3200000 {
reg = <0x03200000 0x800000>;
no-map;
};
mpss@8400000 {
reg = <0x08400000 0x1f00000>;
no-map;
};
mba@a300000 {
reg = <0x0a300000 0x100000>;
no-map;
};
reserved@cb00000 {
reg = <0x0cb00000 0x700000>;
no-map;
};
wcnss@d200000 {
reg = <0x0d200000 0x700000>;
no-map;
};
adsp_region: adsp@d900000 {
reg = <0x0d900000 0x1800000>;
no-map;
};
venus@f100000 {
reg = <0x0f100000 0x500000>;
no-map;
};
smem_region: smem@fa00000 {
reg = <0x0fa00000 0x100000>;
no-map;
};
reserved@fb00000 {
reg = <0x0fb00000 0x260000>;
no-map;
};
rfsa@fd60000 {
reg = <0x0fd60000 0x20000>;
no-map;
};
rmtfs@fd80000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0fd80000 0x180000>;
no-map;
qcom,client-id = <1>;
};
};
};
&adsp {
status = "okay";
};
&blsp1_i2c4 {
status = "okay";
muic: usb-switch@25 {
compatible = "siliconmitus,sm5502-muic";
reg = <0x25>;
interrupt-parent = <&tlmm>;
interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&muic_int_default_state>;
};
};
&blsp1_uart3 {
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm8226-regulators";
pm8226_s3: s3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
};
pm8226_s4: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2200000>;
};
pm8226_s5: s5 {
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
};
pm8226_l1: l1 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
pm8226_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8226_l3: l3 {
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
pm8226_l4: l4 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8226_l5: l5 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8226_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
pm8226_l7: l7 {
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1850000>;
};
pm8226_l8: l8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
pm8226_l9: l9 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
pm8226_l10: l10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8226_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8226_l14: l14 {
regulator-min-microvolt = <2750000>;
regulator-max-microvolt = <2750000>;
};
pm8226_l15: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8226_l16: l16 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3350000>;
};
pm8226_l17: l17 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-system-load = <200000>;
regulator-allow-set-load;
regulator-always-on;
};
pm8226_l18: l18 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
};
pm8226_l19: l19 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3000000>;
};
pm8226_l20: l20 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
pm8226_l21: l21 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8226_l22: l22 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
pm8226_l23: l23 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8226_l24: l24 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1350000>;
};
pm8226_l25: l25 {
regulator-min-microvolt = <1775000>;
regulator-max-microvolt = <2125000>;
};
pm8226_l26: l26 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1300000>;
};
pm8226_l27: l27 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8226_l28: l28 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8226_lvs1: lvs1 {};
};
};
&sdhc_1 {
vmmc-supply = <&pm8226_l17>;
vqmmc-supply = <&pm8226_l6>;
bus-width = <8>;
non-removable;
status = "okay";
};
&sdhc_2 {
vmmc-supply = <&pm8226_l18>;
vqmmc-supply = <&pm8226_l21>;
bus-width = <4>;
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
status = "okay";
};
&tlmm {
accel_int_default_state: accel-int-default-state {
pins = "gpio54";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
backlight_i2c_default_state: backlight-i2c-default-state {
pins = "gpio20", "gpio21";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
backlight_pwm_default_state: backlight-pwm-default-state {
pins = "gpio33";
function = "gp0_clk";
};
muic_int_default_state: muic-int-default-state {
pins = "gpio67";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_en_default_state: tsp-en-default-state {
pins = "gpio31";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_int_rst_default_state: tsp-int-rst-default-state {
pins = "gpio17";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
};
&usb {
extcon = <&muic>, <&muic>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic>;
v1p8-supply = <&pm8226_l10>;
v3p3-supply = <&pm8226_l20>;
};

764
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
View File

@ -20,11 +20,6 @@ / {
chosen { };
memory@0 {
device_type = "memory";
reg = <0x0 0x0>;
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
@ -39,6 +34,57 @@ sleep_clk: sleep_clk {
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
compatible = "arm,cortex-a7";
enable-method = "qcom,msm8226-smp";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
};
CPU1: cpu@1 {
compatible = "arm,cortex-a7";
enable-method = "qcom,msm8226-smp";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
};
CPU2: cpu@2 {
compatible = "arm,cortex-a7";
enable-method = "qcom,msm8226-smp";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
};
CPU3: cpu@3 {
compatible = "arm,cortex-a7";
enable-method = "qcom,msm8226-smp";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
firmware {
scm {
compatible = "qcom,scm-msm8226", "qcom,scm";
@ -47,6 +93,11 @@ scm {
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
@ -185,6 +236,117 @@ apcs: syscon@f9011000 {
reg = <0xf9011000 0x1000>;
};
saw_l2: power-manager@f9012000 {
compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
};
watchdog@f9017000 {
compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt";
reg = <0xf9017000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
clocks = <&sleep_clk>;
};
timer@f9020000 {
compatible = "arm,armv7-timer-mem";
reg = <0xf9020000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
frame@f9021000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
};
acc0: power-manager@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
};
saw0: power-manager@f9089000 {
compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9089000 0x1000>;
};
acc1: power-manager@f9098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
};
saw1: power-manager@f9099000 {
compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9099000 0x1000>;
};
acc2: power-manager@f90a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
};
saw2: power-manager@f90a9000 {
compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90a9000 0x1000>;
};
acc3: power-manager@f90b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
saw3: power-manager@f90b9000 {
compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90b9000 0x1000>;
};
sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
@ -201,22 +363,6 @@ sdhc_1: mmc@f9824900 {
status = "disabled";
};
sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
pinctrl-names = "default";
pinctrl-0 = <&sdhc2_default_state>;
status = "disabled";
};
sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
@ -233,6 +379,22 @@ sdhc_3: mmc@f9864900 {
status = "disabled";
};
sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
pinctrl-names = "default";
pinctrl-0 = <&sdhc2_default_state>;
status = "disabled";
};
blsp1_uart1: serial@f991d000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991d000 0x1000>;
@ -272,7 +434,6 @@ blsp1_uart4: serial@f9920000 {
};
blsp1_i2c1: i2c@f9923000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9923000 0x1000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@ -282,10 +443,10 @@ blsp1_i2c1: i2c@f9923000 {
pinctrl-0 = <&blsp1_i2c1_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp1_i2c2: i2c@f9924000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9924000 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
@ -295,10 +456,10 @@ blsp1_i2c2: i2c@f9924000 {
pinctrl-0 = <&blsp1_i2c2_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp1_i2c3: i2c@f9925000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9925000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@ -308,10 +469,10 @@ blsp1_i2c3: i2c@f9925000 {
pinctrl-0 = <&blsp1_i2c3_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp1_i2c4: i2c@f9926000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9926000 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
@ -321,10 +482,10 @@ blsp1_i2c4: i2c@f9926000 {
pinctrl-0 = <&blsp1_i2c4_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp1_i2c5: i2c@f9927000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9927000 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
@ -334,6 +495,7 @@ blsp1_i2c5: i2c@f9927000 {
pinctrl-0 = <&blsp1_i2c5_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp1_i2c6: i2c@f9928000 {
@ -351,33 +513,6 @@ blsp1_i2c6: i2c@f9928000 {
status = "disabled";
};
cci: cci@fda0c000 {
compatible = "qcom,msm8226-cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfda0c000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
<&mmcc CAMSS_CCI_CCI_AHB_CLK>,
<&mmcc CAMSS_CCI_CCI_CLK>;
clock-names = "camss_top_ahb",
"cci_ahb",
"cci";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cci_default>;
pinctrl-1 = <&cci_sleep>;
status = "disabled";
cci_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
usb: usb@f9a55000 {
compatible = "qcom,ci-hdrc";
reg = <0xf9a55000 0x200>,
@ -417,6 +552,18 @@ usb_hs_phy: phy {
};
};
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
sram@fc190000 {
compatible = "qcom,msm8226-rpm-stats";
reg = <0xfc190000 0x10000>;
};
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8226";
reg = <0xfc400000 0x4000>;
@ -430,146 +577,28 @@ gcc: clock-controller@fc400000 {
"sleep_clk";
};
mmcc: clock-controller@fd8c0000 {
compatible = "qcom,mmcc-msm8226";
reg = <0xfd8c0000 0x6000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
rpm_msg_ram: sram@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_MMSS_GPLL0_CLK_SRC>,
<&gcc GPLL0_VOTE>,
<&gcc GPLL1_VOTE>,
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi0_phy 0>;
clock-names = "xo",
"mmss_gpll0_vote",
"gpll0_vote",
"gpll1_vote",
"gfx3d_clk_src",
"dsi0pll",
"dsi0pllbyte";
};
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc428000 0x4000>;
tlmm: pinctrl@fd510000 {
compatible = "qcom,msm8226-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 117>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
blsp1_i2c1_pins: blsp1-i2c1-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
apss_master_stats: sram@150 {
reg = <0x150 0x14>;
};
blsp1_i2c2_pins: blsp1-i2c2-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
mpss_master_stats: sram@b50 {
reg = <0xb50 0x14>;
};
blsp1_i2c3_pins: blsp1-i2c3-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
lpss_master_stats: sram@1550 {
reg = <0x1550 0x14>;
};
blsp1_i2c4_pins: blsp1-i2c4-state {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c5_pins: blsp1-i2c5-state {
pins = "gpio18", "gpio19";
function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c6_pins: blsp1-i2c6-state {
pins = "gpio22", "gpio23";
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
cci_default: cci-default-state {
pins = "gpio29", "gpio30";
function = "cci_i2c0";
drive-strength = <2>;
bias-disable;
};
cci_sleep: cci-sleep-state {
pins = "gpio29", "gpio30";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
sdhc1_default_state: sdhc1-default-state {
clk-pins {
pins = "sdc1_clk";
drive-strength = <10>;
bias-disable;
};
cmd-data-pins {
pins = "sdc1_cmd", "sdc1_data";
drive-strength = <10>;
bias-pull-up;
};
};
sdhc2_default_state: sdhc2-default-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <10>;
bias-disable;
};
cmd-data-pins {
pins = "sdc2_cmd", "sdc2_data";
drive-strength = <10>;
bias-pull-up;
};
};
sdhc3_default_state: sdhc3-default-state {
clk-pins {
pins = "gpio44";
function = "sdc3";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio43";
function = "sdc3";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio39", "gpio40", "gpio41", "gpio42";
function = "sdc3";
drive-strength = <8>;
bias-pull-up;
};
pronto_master_stats: sram@1f50 {
reg = <0x1f50 0x14>;
};
};
@ -714,170 +743,153 @@ spmi_bus: spmi@fc4cf000 {
#interrupt-cells = <4>;
};
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
timer@f9020000 {
compatible = "arm,armv7-timer-mem";
reg = <0xf9020000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
frame@f9021000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
};
sram@fc190000 {
compatible = "qcom,msm8226-rpm-stats";
reg = <0xfc190000 0x10000>;
};
rpm_msg_ram: sram@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc428000 0x4000>;
apss_master_stats: sram@150 {
reg = <0x150 0x14>;
};
mpss_master_stats: sram@b50 {
reg = <0xb50 0x14>;
};
lpss_master_stats: sram@1550 {
reg = <0x1550 0x14>;
};
pronto_master_stats: sram@1f50 {
reg = <0x1f50 0x14>;
};
};
tcsr_mutex: hwlock@fd484000 {
compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
reg = <0xfd484000 0x1000>;
#hwlock-cells = <1>;
};
adsp: remoteproc@fe200000 {
compatible = "qcom,msm8226-adsp-pil";
reg = <0xfe200000 0x100>;
tlmm: pinctrl@fd510000 {
compatible = "qcom,msm8226-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 117>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
blsp1_i2c1_pins: blsp1-i2c1-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
power-domains = <&rpmpd MSM8226_VDDCX>;
power-domain-names = "cx";
blsp1_i2c2_pins: blsp1-i2c2-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
blsp1_i2c3_pins: blsp1-i2c3-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
memory-region = <&adsp_region>;
blsp1_i2c4_pins: blsp1-i2c4-state {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
blsp1_i2c5_pins: blsp1-i2c5-state {
pins = "gpio18", "gpio19";
function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
status = "disabled";
blsp1_i2c6_pins: blsp1-i2c6-state {
pins = "gpio22", "gpio23";
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
cci_default: cci-default-state {
pins = "gpio29", "gpio30";
function = "cci_i2c0";
qcom,ipc = <&apcs 8 8>;
qcom,smd-edge = <1>;
drive-strength = <2>;
bias-disable;
};
label = "lpass";
cci_sleep: cci-sleep-state {
pins = "gpio29", "gpio30";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
sdhc1_default_state: sdhc1-default-state {
clk-pins {
pins = "sdc1_clk";
drive-strength = <10>;
bias-disable;
};
cmd-data-pins {
pins = "sdc1_cmd", "sdc1_data";
drive-strength = <10>;
bias-pull-up;
};
};
sdhc2_default_state: sdhc2-default-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <10>;
bias-disable;
};
cmd-data-pins {
pins = "sdc2_cmd", "sdc2_data";
drive-strength = <10>;
bias-pull-up;
};
};
sdhc3_default_state: sdhc3-default-state {
clk-pins {
pins = "gpio44";
function = "sdc3";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio43";
function = "sdc3";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio39", "gpio40", "gpio41", "gpio42";
function = "sdc3";
drive-strength = <8>;
bias-pull-up;
};
};
};
sram@fdd00000 {
compatible = "qcom,msm8226-ocmem";
reg = <0xfdd00000 0x2000>,
<0xfec00000 0x20000>;
reg-names = "ctrl", "mem";
ranges = <0 0xfec00000 0x20000>;
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>;
clock-names = "core";
mmcc: clock-controller@fd8c0000 {
compatible = "qcom,mmcc-msm8226";
reg = <0xfd8c0000 0x6000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
gmu_sram: gmu-sram@0 {
reg = <0x0 0x20000>;
};
};
sram@fe805000 {
compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
reg = <0xfe805000 0x1000>;
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x65c>;
mode-bootloader = <0x77665500>;
mode-normal = <0x77665501>;
mode-recovery = <0x77665502>;
};
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_MMSS_GPLL0_CLK_SRC>,
<&gcc GPLL0_VOTE>,
<&gcc GPLL1_VOTE>,
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi0_phy 0>;
clock-names = "xo",
"mmss_gpll0_vote",
"gpll0_vote",
"gpll1_vote",
"gfx3d_clk_src",
"dsi0pll",
"dsi0pllbyte";
};
mdss: display-subsystem@fd900000 {
@ -1007,6 +1019,33 @@ mdss_dsi0_phy: phy@fd922a00 {
};
};
cci: cci@fda0c000 {
compatible = "qcom,msm8226-cci";
reg = <0xfda0c000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
<&mmcc CAMSS_CCI_CCI_AHB_CLK>,
<&mmcc CAMSS_CCI_CCI_CLK>;
clock-names = "camss_top_ahb",
"cci_ahb",
"cci";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cci_default>;
pinctrl-1 = <&cci_sleep>;
status = "disabled";
cci_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
gpu: adreno@fdb00000 {
compatible = "qcom,adreno-305.18", "qcom,adreno";
reg = <0xfdb00000 0x10000>;
@ -1046,6 +1085,71 @@ opp-19000000 {
};
};
};
sram@fdd00000 {
compatible = "qcom,msm8226-ocmem";
reg = <0xfdd00000 0x2000>,
<0xfec00000 0x20000>;
reg-names = "ctrl", "mem";
ranges = <0 0xfec00000 0x20000>;
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <1>;
gmu_sram: gmu-sram@0 {
reg = <0x0 0x20000>;
};
};
adsp: remoteproc@fe200000 {
compatible = "qcom,msm8226-adsp-pil";
reg = <0xfe200000 0x100>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
power-domains = <&rpmpd MSM8226_VDDCX>;
power-domain-names = "cx";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
memory-region = <&adsp_region>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 8>;
qcom,smd-edge = <1>;
label = "lpass";
};
};
sram@fe805000 {
compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
reg = <0xfe805000 0x1000>;
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x65c>;
mode-bootloader = <0x77665500>;
mode-normal = <0x77665501>;
mode-recovery = <0x77665502>;
};
};
};
thermal-zones {

17
arch/arm/boot/dts/qcom/qcom-msm8660.dtsi
View File

@ -47,7 +47,7 @@ memory {
cpu-pmu {
compatible = "qcom,scorpion-mp-pmu";
interrupts = <1 9 0x304>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
@ -89,12 +89,11 @@ intc: interrupt-controller@2080000 {
timer@2000000 {
compatible = "qcom,scss-timer", "qcom,msm-timer";
interrupts = <1 0 0x301>,
<1 1 0x301>,
<1 2 0x301>;
interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x02000000 0x100>;
clock-frequency = <27000000>,
<32768>;
clock-frequency = <27000000>;
cpu-offset = <0x40000>;
};
@ -105,7 +104,7 @@ tlmm: pinctrl@800000 {
gpio-controller;
gpio-ranges = <&tlmm 0 0 173>;
#gpio-cells = <2>;
interrupts = <0 16 0x4>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@ -283,7 +282,7 @@ gsbi12_serial: serial@19c40000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@ -292,7 +291,7 @@ gsbi12_serial: serial@19c40000 {
gsbi12_i2c: i2c@19c80000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x19c80000 0x1000>;
interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;

15
arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts
View File

@ -107,7 +107,20 @@ smem_region: smem@fa00000 {
};
unknown@fb00000 {
reg = <0x0fb00000 0x1b00000>;
reg = <0x0fb00000 0x280000>;
no-map;
};
rmtfs@fd80000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0fd80000 0x180000>;
no-map;
qcom,client-id = <1>;
};
unknown@ff00000 {
reg = <0x0ff00000 0x1700000>;
no-map;
};
};

37
arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts Normal file
View File

@ -0,0 +1,37 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com>
* Copyright (c) 2023, Stefan Hansson <newbyte@postmarketos.org>
*/
/dts-v1/;
#include "qcom-msm8226-samsung-matisse-common.dtsi"
/ {
model = "Samsung Galaxy Tab 4 10.1 LTE";
compatible = "samsung,matisselte", "qcom,msm8926", "qcom,msm8226";
chassis-type = "tablet";
reg_tsp_3p3v: regulator-tsp-3p3v {
compatible = "regulator-fixed";
regulator-name = "tsp_3p3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&tsp_en1_default_state>;
};
};
&tlmm {
tsp_en1_default_state: tsp-en1-default-state {
pins = "gpio32";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};

21
arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-only
&msmgpio {
i2c3_default_state: i2c3-default-state {
i2c3-pins {
pins = "gpio16", "gpio17";
function = "gsbi3";
drive-strength = <8>;
bias-disable;
};
};
i2c3_sleep_state: i2c3-sleep-state {
i2c3-pins {
pins = "gpio16", "gpio17";
function = "gpio";
drive-strength = <2>;
bias-bus-hold;
};
};
};

71
arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts
View File

@ -4,6 +4,9 @@
#include "qcom-msm8960.dtsi"
#include "pm8921.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/input/gpio-keys.h>
/ {
model = "Samsung Galaxy Express SGH-I437";
@ -19,6 +22,36 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;
key-home {
label = "Home";
gpios = <&msmgpio 40 GPIO_ACTIVE_LOW>;
debounce-interval = <5>;
linux,code = <KEY_HOMEPAGE>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
};
key-volume-up {
label = "Volume Up";
gpios = <&msmgpio 50 GPIO_ACTIVE_LOW>;
debounce-interval = <5>;
linux,code = <KEY_VOLUMEUP>;
};
key-volume-down {
label = "Volume Down";
gpios = <&msmgpio 81 GPIO_ACTIVE_LOW>;
debounce-interval = <5>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
&gsbi5 {
@ -52,6 +85,27 @@ &gsbi1_spi {
status = "okay";
};
&gsbi3 {
qcom,mode = <GSBI_PROT_I2C>;
status = "okay";
};
&gsbi3_i2c {
status = "okay";
// Atmel mXT224S touchscreen
touchscreen@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&msmgpio>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
vdda-supply = <&pm8921_lvs6>;
vdd-supply = <&pm8921_l17>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen>;
};
};
&msmgpio {
spi1_default: spi1-default-state {
mosi-pins {
@ -83,6 +137,21 @@ clk-pins {
bias-disable;
};
};
gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio40", "gpio50", "gpio81";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
touchscreen: touchscreen-int-state {
pins = "gpio11";
function = "gpio";
output-enable;
bias-disable;
drive-strength = <2>;
};
};
&pm8921 {
@ -245,7 +314,7 @@ pm8921_l16: l16 {
};
pm8921_l17: l17 {
regulator-min-microvolt = <1800000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
bias-pull-down;
};

48
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
View File

@ -220,16 +220,24 @@ acc1: clock-controller@2098000 {
#clock-cells = <0>;
};
saw0: regulator@2089000 {
compatible = "qcom,saw2";
saw0: power-manager@2089000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
saw0_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
saw1: regulator@2099000 {
compatible = "qcom,saw2";
saw1: power-manager@2099000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
saw1_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
gsbi5: gsbi@16400000 {
@ -359,5 +367,33 @@ usb_hs1_phy: phy {
};
};
};
gsbi3: gsbi@16200000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16200000 0x100>;
ranges;
cell-index = <3>;
clocks = <&gcc GSBI3_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
gsbi3_i2c: i2c@16280000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16280000 0x1000>;
pinctrl-0 = <&i2c3_default_state>;
pinctrl-1 = <&i2c3_sleep_state>;
pinctrl-names = "default", "sleep";
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI3_QUP_CLK>,
<&gcc GSBI3_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
};
#include "qcom-msm8960-pins.dtsi"

33
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
View File

@ -31,7 +31,7 @@ sleep_clk: sleep_clk {
cpus {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_PPI 9 0xf04>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
CPU0: cpu@0 {
compatible = "qcom,krait";
@ -110,7 +110,7 @@ memory {
pmu {
compatible = "qcom,krait-pmu";
interrupts = <GIC_PPI 7 0xf04>;
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
rpm: remoteproc {
@ -346,10 +346,9 @@ apcs: syscon@f9011000 {
reg = <0xf9011000 0x1000>;
};
saw_l2: power-controller@f9012000 {
compatible = "qcom,saw2";
saw_l2: power-manager@f9012000 {
compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
regulator;
};
watchdog@f9017000 {
@ -424,7 +423,7 @@ acc0: power-manager@f9088000 {
reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
};
saw0: power-controller@f9089000 {
saw0: power-manager@f9089000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
};
@ -434,7 +433,7 @@ acc1: power-manager@f9098000 {
reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
};
saw1: power-controller@f9099000 {
saw1: power-manager@f9099000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
};
@ -444,7 +443,7 @@ acc2: power-manager@f90a8000 {
reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
};
saw2: power-controller@f90a9000 {
saw2: power-manager@f90a9000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
};
@ -454,7 +453,7 @@ acc3: power-manager@f90b8000 {
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
saw3: power-controller@f90b9000 {
saw3: power-manager@f90b9000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
};
@ -538,7 +537,7 @@ blsp1_i2c1: i2c@f9923000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9923000 0x1000>;
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
@ -566,7 +565,7 @@ blsp1_i2c3: i2c@f9925000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9925000 0x1000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
@ -666,7 +665,7 @@ blsp2_i2c6: i2c@f9968000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9968000 0x1000>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
@ -1234,7 +1233,7 @@ restart@fc4ab000 {
qfprom: qfprom@fc4bc000 {
compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
reg = <0xfc4bc000 0x1000>;
reg = <0xfc4bc000 0x2100>;
#address-cells = <1>;
#size-cells = <1>;
@ -2403,10 +2402,10 @@ gpu2_alert0: trip-point0 {
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 2 0xf08>,
<GIC_PPI 3 0xf08>,
<GIC_PPI 4 0xf08>,
<GIC_PPI 1 0xf08>;
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
};

18
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
View File

@ -731,57 +731,57 @@ timer@17820000 {
frame@17821000 {
frame-number = <0>;
interrupts = <GIC_SPI 7 0x4>,
<GIC_SPI 6 0x4>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17821000 0x1000>,
<0x17822000 0x1000>;
};
frame@17823000 {
frame-number = <1>;
interrupts = <GIC_SPI 8 0x4>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17823000 0x1000>;
status = "disabled";
};
frame@17824000 {
frame-number = <2>;
interrupts = <GIC_SPI 9 0x4>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17824000 0x1000>;
status = "disabled";
};
frame@17825000 {
frame-number = <3>;
interrupts = <GIC_SPI 10 0x4>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17825000 0x1000>;
status = "disabled";
};
frame@17826000 {
frame-number = <4>;
interrupts = <GIC_SPI 11 0x4>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17826000 0x1000>;
status = "disabled";
};
frame@17827000 {
frame-number = <5>;
interrupts = <GIC_SPI 12 0x4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17827000 0x1000>;
status = "disabled";
};
frame@17828000 {
frame-number = <6>;
interrupts = <GIC_SPI 13 0x4>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17828000 0x1000>;
status = "disabled";
};
frame@17829000 {
frame-number = <7>;
interrupts = <GIC_SPI 14 0x4>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17829000 0x1000>;
status = "disabled";
};

34
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
View File

@ -492,10 +492,10 @@ usb: usb@a6f8800 {
clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_USB30_MSTR_AXI_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep";
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
clock-names = "cfg_noc", "core", "iface", "sleep",
"mock_utmi";
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
@ -669,57 +669,57 @@ timer@17820000 {
frame@17821000 {
frame-number = <0>;
interrupts = <GIC_SPI 7 0x4>,
<GIC_SPI 6 0x4>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17821000 0x1000>,
<0x17822000 0x1000>;
};
frame@17823000 {
frame-number = <1>;
interrupts = <GIC_SPI 8 0x4>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17823000 0x1000>;
status = "disabled";
};
frame@17824000 {
frame-number = <2>;
interrupts = <GIC_SPI 9 0x4>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17824000 0x1000>;
status = "disabled";
};
frame@17825000 {
frame-number = <3>;
interrupts = <GIC_SPI 10 0x4>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17825000 0x1000>;
status = "disabled";
};
frame@17826000 {
frame-number = <4>;
interrupts = <GIC_SPI 11 0x4>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17826000 0x1000>;
status = "disabled";
};
frame@17827000 {
frame-number = <5>;
interrupts = <GIC_SPI 12 0x4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17827000 0x1000>;
status = "disabled";
};
frame@17828000 {
frame-number = <6>;
interrupts = <GIC_SPI 13 0x4>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17828000 0x1000>;
status = "disabled";
};
frame@17829000 {
frame-number = <7>;
interrupts = <GIC_SPI 14 0x4>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17829000 0x1000>;
status = "disabled";
};
@ -806,10 +806,10 @@ apps_bcm_voter: bcm-voter {
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 12 0xf08>,
<1 10 0xf08>,
<1 11 0xf08>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
};

41
arch/arm/mach-qcom/Kconfig
View File

@ -4,46 +4,21 @@ menuconfig ARCH_QCOM
depends on ARCH_MULTI_V7
select ARM_GIC
select ARM_AMBA
select CLKSRC_QCOM
select HAVE_ARM_ARCH_TIMER
select PINCTRL
select QCOM_SCM if SMP
help
Support for Qualcomm's devicetree based systems.
This includes support for a few devices with ARM64 SoC, that have
ARM32 signed firmware that does not allow booting ARM64 kernels.
if ARCH_QCOM
config ARCH_IPQ40XX
bool "Enable support for IPQ40XX"
select CLKSRC_QCOM
select HAVE_ARM_ARCH_TIMER
config ARCH_MSM8X60
bool "Enable support for MSM8X60"
select CLKSRC_QCOM
config ARCH_MSM8909
bool "Enable support for MSM8909"
select HAVE_ARM_ARCH_TIMER
config ARCH_MSM8916
bool "Enable support for MSM8916"
select HAVE_ARM_ARCH_TIMER
config ARCH_QCOM_RESERVE_SMEM
bool "Reserve SMEM at the beginning of RAM"
help
Enable support for the Qualcomm Snapdragon 410 (MSM8916/APQ8016).
Note that ARM64 is the main supported architecture for MSM8916.
The ARM32 option is intended for a few devices with signed firmware
that does not allow booting ARM64 kernels.
config ARCH_MSM8960
bool "Enable support for MSM8960"
select CLKSRC_QCOM
config ARCH_MSM8974
bool "Enable support for MSM8974"
select HAVE_ARM_ARCH_TIMER
config ARCH_MDM9615
bool "Enable support for MDM9615"
select CLKSRC_QCOM
Reserve 2MB at the beginning of the System RAM for shared mem.
This is required on IPQ40xx, MSM8x60 and MSM8960 platforms.
endif

2
drivers/iommu/Kconfig
View File

@ -179,7 +179,7 @@ config FSL_PAMU
config MSM_IOMMU
bool "MSM IOMMU Support"
depends on ARM
depends on ARCH_MSM8X60 || ARCH_MSM8960 || COMPILE_TEST
depends on ARCH_QCOM || COMPILE_TEST
select IOMMU_API
select IOMMU_IO_PGTABLE_ARMV7S
help